[XST 8.2.3] DSP48 inference multiply/add

I'm not 100% sure, but I suspect it's because you are using std_logic_unsigned and consequently implying 18x18 UNSIGNED multipliers, whereas the DSP48 blocks have

The easy way to check this theory is to tweak the design so that all the inputs are 17 bits instead of 18 bits wide. If, as I suspect, this then gives you just the one DSP48, then I'm right and either you need to make everything signed or you need to reconsider how to do the DSP.

Apologies if this is a wild goose chase.

indeed, that is also what i thought and when i use it on the template:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all;

entity multadd is generic ( a_width : integer :=18; b_width : integer :=18; c_width : integer :=35 ); port ( ce : in std_logic; reset : in std_logic; clk : in std_logic; a : in std_logic_vector((a_width - 1) downto 0); b : in std_logic_vector((b_width - 1) downto 0); c : in std_logic_vector((c_width - 1) downto 0); p_out : out std_logic_vector((c_width - 1) downto 0) ); end multadd;

architecture rtl of multadd is

signal a_reg : std_logic_vector((a_width - 1) downto 0); signal b_reg : std_logic_vector((b_width - 1) downto 0); signal c_align : std_logic_vector((c_width - 1) downto 0); signal c_reg : std_logic_vector((c_width - 1) downto 0); signal m_reg : std_logic_vector((a_width + b_width - 1) downto 0);

begin

multadd_proc : process(clk) begin if (clk'event and clk = '1') then if (reset = '1') then a_reg '0'); b_reg '0'); c_align '0'); c_reg '0'); m_reg '0'); p_out '0'); elsif (ce = '1') then a_reg i have this piece of code where i want to use the multiply/add

ok, your right, now i know why it works on this code and not mine, in the template i used the following libraries:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all;

and in mine i used

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

and yes it has to do with the unsigned/signed library ...

thanks for pointing that out and making me look again at that part of the code ...

kind regards,

Tim

Tim Verstraete schreef:

And that is PRECISELY why I keep banging on about why STD_LOGIC_(UN)SIGNED is such a very, very bad thing.

If you had used only STD_LOGIC_ARITH or (better) NUMERIC_STD, then you would have been forced into declaring the objects as SIGNED or UNSIGNED, and you would know what you were doing. Having an arbitrary numeric representation imposed on std_logic_vector by a use clause is IMO certifiably insane.

Thanks for providing more ammunition for my rant :-)

These newsgroups provide plenty of this sort of ammunition. The source, it seems to me, is the training examples and editor templates from brand X and brand S.

The result is that most designers of VHDL synthesis code are convinced that using signed and unsigned types is a waste of time, and that only "purists" think otherwise.

This state of affairs is only a problem for me when I use or supply entities to other designers. My workaround in this case is to declare [un]signed variables for use in my entity and implicit type conversion for port input and output assignments from the omnipresent std_logic_vector type.

-- Mike Treseler

Indeed. Furthermore, at least half the time, having included the std_logic_arith type libraries, the code doesn't ever use them!

It is normal practice for me to comment out these "use" clauses; normally the code just compiles without them, and I have one less thing to worry about. (In the rare examples that actually use them, it's not usually difficult to make them numeric_std clean, though I don't always bother)

- Brian

By the same token, if you do a lot of DSP, you'll soon learn to appreciate the strong typing in VHDL as compared to verilog, and may even grow to despise the permissiveness (and ambiguity) of verilog.

FWIW, I code my VHDL components with std_logic and std_logic_vector on the I/O in order to be consistent with existing libraries. I convert the signals to signed/unsigned inside the architecture as needed. Some of my components have a boolean generic, "is_signed" to specify the behavior as an option.