Hi all, I'm trying to develop a core that is connected to the PLB bus and uses FIFO to communicate to the PPC. The FPGA I'm using is a virtex2pro on a XUP board. When I go through the process to create a new device and I select "VHDL" stub everything seem to work fine and the self test returns the expected results. When instead I use the verilog stub i got this result:
Running FIFO_SelfTest() for LEDs_4Bit...
******************************- User Peripheral Self Test
RST/MIR test... - write 0x0000000A to software reset register - read 0x10050308 (expected) from module identification register - RST/MIR write/read passed
User logic slave module test... - write 1 to slave register 0 upper and lower portion - read 1, 1 from register 0 upper and lower portion - write 2 to slave register 1 upper and lower portion - read 2, 2 from register 1 upper and lower portion - slave register write/read passed
User logic BRAM test... - local BRAM address is 0xCDE00000 - write pattern to local BRAM and read back - write/read BRAM failed on address 0xCDE00000 FIFO_SelfTest FAILED.
The XPS I use is 9.1i.
Does anyone else get this message before? I'm quite sure that I set correctly all the memory addresses in the HW modules and in the drivers. Thanks ~Andrea