After designing a peripheral and checking that it is working with the BFM simulation, I am trying to simulate the whole system. I created a simple system with BSB in order to get experience with this simulation. I generated the Hdl libraries in XPS and modified the modelsim.ini to use the Smartmodels ( I use Modelsim SE PLUS 6.2a). I also checked it with: VSIM>vsim unisim.ppc405 And it is working ok.
XPS creates the directory simulation/behavior with the scripts to simulate the system in Modelsim. The system was compiled using these scripts.
I have an error while the system is loaded:
# Loading opb_arbiter_v1_02_e.or_gate(imp)#1 # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32) for port '/system/opb/opb/opb_abus_i/y'. # Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/ opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125 # FATAL ERROR while loading design # Error loading design # 1
I do not how to solve this problem as the opb_arbiter_v1_02_e module is a Xilinx IP core, and it is read only. It has to be any solution, because some people are using this kind of simulation and I am trying to use it with a simple design created with BSB( bitstream ok, and the software project is the default TestAppMemory)
Can anyone help me, thanks.
Note: This is almost all the information of Modelsim # vsim -t ps system_conf # Loading /opt/modeltech/6.2a/linux/libswiftpli.sl # Loading /opt/modeltech/6.2a/linux/../std.standard # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_1164(body) ... ... ... # Loading /opt/modeltech/6.2a/linux/libsm.sl # ** Note (SmartModel): # Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED # ** Note (SmartModel): # Platform Type: x86_linux (32-bit). # ** Note (SmartModel): # You can use the Browser tool to configure the SmartModel # Library and access information about SmartModels: # $LMC_HOME/bin/sl_browser # # SmartModel product documentation is available here: # $LMC_HOME/doc/smartmodel/manuals/intro.pdf #