Hi, Im woerking on a Xilinx Virtex-II pro with Xilinx Platform Studio 7.1
My design has a bidirectional 8-bits bus. If I synthesize with Project Navigator and then I download the result using impact. everything works without any problem.
I tried to integrate the design in a custom IP and i got this error during the synthesis:
ERROR:Xst:759 - "c:/xps2/synthesis/../hdl/opbusblogic_0_wrapper.vhd" line 94: No default binding for component: . Ports are not on the entity.
It seems that the original design
port( ... data_bus: inout std_logic_vector(7 downto 0); ...);
has been converted in
port( ... data_bus_I : in std_logic_vector(7 downto 0); data_bus_O : out std_logic_vector(7 downto 0); data_bus_T : out std_logic; ...);
of course, these three signals are not defined in my design.
What can I do?
Thans, Ivano.