XMD : Running XMD with Caches on

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Hello,

I would like to know whether turning on the caches in the PPC influences the
functionality of XMD.

1) For instance, when XMD downloads an ELF binary to the memory, it issues
writes to processor through the debug ports. Is it safe to assume that these
writes bypass the data cache? If this wasn't the case and you are using a
writeback cache setting, then there is a chance that the instructions wouldn't
make it to main memory. Thus, when executing the program, the instructions won't
be read by the processor because it searches the instruction cache, then main
memory on a miss. Does this make sense?

2) When using the debug mrd (memory read) or mwr (memory write), is it safe to
assume that the data cache is bypassed since it is a debug memory read/write,
even if the address actually resides in the cache? If the debug read/write does
search the cache and causes a miss, will the configured cache behavior ensue
(like fetching the rest of the cache line on a miss)? If this is the case, then
debug reads could change the state of the cache/memory, which may not be desired
by the programmer.

In general, I would like to understand the mechanism that XMD uses to issue
writes/reads to the processor for both instruction download and debug memory
read/writes. The "PowerPC Processor Reference Guide" goes into nice detail about
the debug capabilities of the PPC 405 with the various configuration registers
and signals. However, there is no documentation (that I have found) that
discusses how XMD employs those debug features. Therefore, I don't know if XMD
is configuring the caches to go into non-cacheable mode for the debug memory
accesses or it uses the existing configuration as defined by the program.

I'm working on a ML 310 board with a V2P30 -6 chip.

NN

Re: XMD : Running XMD with Caches on
Nju,

XMD keeps the main memory consistent with the contents of the caches and
vice versa. Debugging with caches on and/or off works in a consistent
way and with guaranteed integrity of the data/code in the caches and the
memory.

- Peter


Njuguna Njoroge wrote:
Quoted text here. Click to load it
functionality of XMD.
Quoted text here. Click to load it
writes to processor through the debug ports. Is it safe to assume that these
writes bypass the data cache? If this wasn't the case and you are using a
writeback cache setting, then there is a chance that the instructions wouldn't
make it to main memory. Thus, when executing the program, the instructions won't
be read by the processor because it searches the instruction cache, then main
memory on a miss. Does this make sense?
Quoted text here. Click to load it
assume that the data cache is bypassed since it is a debug memory read/write,
even if the address actually resides in the cache? If the debug read/write does
search the cache and causes a miss, will the configured cache behavior ensue
(like fetching the rest of the cache line on a miss)? If this is the case, then
debug reads could change the state of the cache/memory, which may not be desired
by the programmer.
Quoted text here. Click to load it
writes/reads to the processor for both instruction download and debug memory
read/writes. The "PowerPC Processor Reference Guide" goes into nice detail about
the debug capabilities of the PPC 405 with the various configuration registers
and signals. However, there is no documentation (that I have found) that
discusses how XMD employs those debug features. Therefore, I don't know if XMD
is configuring the caches to go into non-cacheable mode for the debug memory
accesses or it uses the existing configuration as defined by the program.
Quoted text here. Click to load it


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