Hi, I've been working on a simulink model built using the Xilinx Blockset to try to verify the function of an interplation filter made from the MacFir Core. The full working VHDL version of the complete data path where the input data goes into a fifo and is read out to the filter as it is ready for data. The filter does a simple up by 2 interpolation and the output data is written to another fifo for eventual output. This filter actually handles 64 channels. The input rate for the data is 100KHz and the Output rate is to be
200KHz. In my simulink model I read the data for a input signal consisting of 2 sine waves, one well within the filters passband and one in the stop band, from the MATLAB workspace. I then multiplex that same data to 28 channels and feed the filter which is intantiated in the Simulink model as a black box as per Matlab's help file for inserting a Xilinx core into a model. I've had a lot of confusion about sample rates and how to deal with them in Simulink, but I think I'm finally getting the hang of them. The output rate is 2x the input rate for the complete system - fifo in to fifo out but the filter runs very fast compared to the actual data rate in and out. The Modelsim simulation of the whole VHDL coded system seems to be working- I get 2 samples out for every one in on all the channels and the data is written to the output fifos ok. Since the data is fixed point I wanted to verify my output values with what I get in the Simulink model which uses the fixed point blockset etc. The biggest issue I have is that the Modelsim simulation goes very fast and outputs data from the filter every usec or less while the Simulink model using the Modelsim output block takes milliseconds to produce an output data. It does give me 2 values for every one in and the filter model appears to be working ok, but the clocking of the whole model is running at a sample rate of 100KHz. . I use modelsim under the control of Simulink to run the simulation and the fastest clock in the simulation is 200KHz. The system clock in the "real" VHDL system is 80MHz. When I try to increase the system clock in the SystemGenerator block to anything faster than 1MHz I get some error about an unresolved Boolean value and the simulation doesn't run. Has anyone matched what an actual synthesizable system to a Simulink model at the actual clock rates used in the VHDL simulation? When I look at all the example files for simulink it seems they always use sample rates of 1sec which seems ridiculous when trying to match clock rates in an FPGA system. Am I really off the mark here or to I just have to run my Simulink model for 45 minutes to match what the VHDL model gives me in 2 seconds?Totally dazed and confused,
CTW