Xilinx XST synthesis removes input pin even though it's LOCed

Synthesisers usually remove unused inputs. One crude way that works with all synthesiser is to use the unused inputs in a dummy function. This dummy function must be used somewhere but if you make it so that is always '1' or '0' and use that value where you don't care then that will be enough. If you have a spare pin you can always attached the function to that.

A typical dummy function might be an OR gate of all unused signals possibly with some real signals as well to ensure a always '1' output. Similarly use AND gate for '0'.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

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Hi,

Have a look at the SAVE NET FLAG constraint in the cgd.pdf documentation.

Regards, Alvin.

Using LOC and SAVE NET FLAG with no results. The PARer gives the warnings: "logical net on "signal" has no load" and "Attribute LOC on "signal" is on the wrong type of object."

Then looking at the project.pad_txt file, "signal" does not show up.

I thought about using the dummy function, but the inputs are just discrete interrupts from outside that update a register that gets read/reset at some later time. What better 'dummy' funtion? I can see how it could get optimized out, but those inputs are needed whether XST thinks they are or not.

Reading the docs leads me to believe the SAVE NET FLAG should do the job, but..... Thanks again for the suggestions. Knowing where to find that doc is worth the post!

I would check that the register isn't being removed. A synthesiser will tend to remove anything that it thinks unused or unconnected.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

documentation.