Hi, I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in Unit ..." It's a wire in a submodule and i checked the code: The signal is an output to module A and an input to module B. There is no other assignment to this signal. Inside module B the signal is only on the right-side of any "=" assignments.
Could there be a bug in Xst when using a design containig both VHDL and verilog files?
Timo