xilinx xc9536?

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Hello, there are some pins on xilinx xc9536 which are called global
clock1/2/3
global reset, etc, where are these explained?



Re: xilinx xc9536?
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There's a document called something like "XC9500 device family datasheet".
Those pins are (optionally) connected to special internal routing resources
that make them suitable for use as input clocks and global set/reset.
Isn't there also a global tristate?

--
Ben Jackson AD7GD
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Re: xilinx xc9536?
Look at
http://direct.xilinx.com/bvdocs/publications/ds064.pdf
pin-outs on page 6
Peter Alfke

On Dec 31, 10:18 am, <highZ> wrote:
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Re: xilinx xc9536?

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This is true, page 6 shows which pins are which. But what I was
asking is different -- what is the reason for these pins, when do
we use them, what do they do?

For example, I can connect an oscillator to any IO pin, which
can then be used in statements like

always @ (posedge input-pin)


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Re: xilinx xc9536?
My rule is:
Use the smallest possible number of different clock signals (one is
best) and use the tight global clock distribution to avoid hold-time
issues altogether, and also to achieve highest performance.
And, last not least, simplify the debugging process.
The problems you will encounter and the time to resolve them, are both
proportional to the number of different clocks you are using. But maybe
it's a third-power relationship  ;-)
Peter Alfke

On Jan 1, 1:27 pm, <highZ> wrote:
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I was
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Re: xilinx xc9536?
H-Z,

Dedicated pins are used to offer some benefit that would not be
available from a general purpose pin.  For example, a clock should have
less delay than any other signal, or else you would need to worry that
the clock might arrive after the data.  Thus dedicated clock pins have
lower skew than other pins.  By using the dedicated clocks, the internal
routing is never an issue.  If you used some other general purpose
resource for a clock, then setup and hold times must be met everywhere
that signal might go and get used.

A reset pin might have additional logic on it, to prevent glitching if a
clock occurs simultaneous with the reset.

It is all in the data sheets, and user's guides:  really.

Austin

Re: xilinx xc9536?
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Which one, there are many datasheets for the 9500 familiy and
for each specific one. I had a glance at all of them and couldn't
see all these things. What exactly does 'reset' do in the first
place, well I will see again if I can find it. Thanks

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Re: xilinx xc9536?
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If you're really so unwilling to read the datasheets, you are doomed.

--
Ben Jackson AD7GD
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Re: xilinx xc9536?
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I probably spend up to 1/2 my working life (and some of my supposedly
non-working life) , perhaps more, reading datasheets to understand and
effectively use devices.

For this particular part and issue (I use the XC9536XL in 3 designs and
I avail myself of the GCLKs for various reasons) all is indeed
explained in the following places:

1. The family datasheet (XC9500 series) has the overview and timings,
which can vary with package.

2. The device datasheet (XC9536)

3. The various application notes available on the Xilinx site.

If you wish to do this stuff successfully, you have to be willing to
absorb an inordinate amount of data from datasheets.

If you don't wish to do the work of looking, reading and
*understanding*, then our help would be futile anyway.

Cheers

PeteS

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Re: xilinx xc9536?
As I said, I did look, but coudn't find

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Re: xilinx xc9536?
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I don't have the datasheets in front of me, but here's a suggestion:

Go to

htttp://www.xilinx.com/

Get to the XL9536 page:

Look for 'application notes'

I am sure there's one on using GCLK

Cheers

PeteS

Re: xilinx xc9536?
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CPLD data is not the most user friendly, and can give the impression
they do not chase new users.

For Xilinx, look at both the pdf called "XC9500 In-System Programmable
CPLD Family", and also the device data sheet, and you do need to make
the odd leap.

Fig 1 has some overview,  Fig 3, Fig4  have more details.

In fig 1,  GCK is tagged as 3 lines, and Data Sheet PIN map shows GCK1,
GCK2,  GCK3 Fig4 shows how those GCKx lines feed all FF's (Fig 3 calls
them Global Clocks)

Most common Macrocell resource ( CLK, SET, RESET in 9536 case) have the
choice of Global, or Product Term drive. Pin resource also has Global
OE, but called  GTSx in some places, and Global OE in others (see Fig
10)

GSR can map to either SET or RESET, so you can use one gobal signal, to
load one initial pattern into your macrocells  (any mix of 1's and 0's
)

Both Global and PT drive work, but Global is faster and uses less
product terms, so is preferred. Usually you move from using Global only
when they are all committed.

The fitter will choose Global, if given the choice.

Write some code both ways: map CLK to a GCK1 pin, and to a IO pin , and
compare the
Fitter report files.(IIRC Xilinx tag these DesignName.RPT)

You will need to be able to read and understand the fitter report
files, but the compile/fit process is fast, so when faced with
questions like this again, just try it both ways, and
look at the fitter report, to see what the final nett effect is.

-jg


Re: xilinx xc9536?
I feel sorry for anyone who does not know what "reset" means, and then
tries to make sense of a halfway-modern CPLD (or FPGA) data sheet.
These data sheets are really written for the knowledgeable engineer;
they are not a basic tutorial. For that there are many textbooks.
Our industry (CPLD and FPGA) is now over 25 years old, and we cannot
let every data sheet go back to square one. That would bore the serious
designers to death.
I am a fan of tutorial information, and I try to sneak explanations in
whenever I see a need. But there is a limit.
Our data sheets will not explain the function of a master-slave
D-flip-flop and its clocking and reset and preset (except saying
whether it is synchronou or asynchronous, and which one overrides the
other.)
The fundamentals are up to schools and universities and libraries to
convey.
Peter Alfke, Xilinx Applications


On Jan 2, 9:23 pm, snipped-for-privacy@gmail.com wrote:
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most user friendly, and can give the impression
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