A customer wants to input 10 bit data into a Xilinx Virtex-II at 800MHz. I've looked at XAPP265 which suggests that this should be possible, albeit with some effort. This seems to REAL close to the limit that the Xilinx parts could handle.
Looking at the Altera "true-LVDS" pads, it seems like they may have a cleaner / more robust solution for this.
Has anyone actually had experience doing this with a Xilinx Virtex-II or an Altera part? Any horror stories or other tips?
Clearly, all the usual (unusual??) care with board layout, pin assignment, etc. is needed.
Here are a few pointers (and yes we have done it, and tested it, but I can not speak for customers):
1) use IOBs that are best for clock skew to minimize that issue. These are left and right sides, adjacent, working out from the center. Using this topology, the hclk skew can be kept to less than ~ 50 ps.
2) get the flight time maps for the package you wish to use, so that pcb trace skew, package skew, can all be kept to less than 5 or 10 ps. There is a per bit deskew core that we offer, and this may also be a chosie you should consider, as it makes the layout, etc a lot easier.
3) use dynamic alignment (either our IP cores, or your own design) which will automatically find and keep the data in the center of the eye
4) be extremely careful with single ended IO switching (causes ground bounce which will cause jitter) be sure that all single ended IOs are keep away from the LVDS pairs
5) have to probably use faster speed grade than -4. I know of many designs using ~ 700 Mbs with -5 speed grade parts. You may want to consider V2P for this instead, (faster).
6) keep the design synchronous (ie one clock is used for all timing, or all clocks are related (ie x2, /2, /3, etc).
7) use the fixed phase shift to shift offending single ended IO switching away from the sample point of the LVDS eye, also good for large amounts of switching CLBs, too. This places the clock edge for logic and single ended IOs where the ground bounce will not interfere with the LVDS. Typical phase whift is ~270 degrees to ~300 degrees (or -60 to -90 degrees).
8) use two BUFG trees: one for clk0, and one for clk180 to minimize duty cycle distortion (also directly takes away from the timing budget)
9) all IO is done with DDR FF in the IOB
Also check out the SPI POS 4 cores, and similar high speed cores in our IP lounge.
800 Mbs is no easy task, regardless of the chip. This is also known as "microwave" in some communities, and the signal integrity, pcb layout, and all the rest is as much or more of a challenge than the FPGA part of it.
This is precisely why the MGTs (high speed gigabit serializer-deserializers) are becoming so popular.
Aust> A customer wants to input 10 bit data into a Xilinx Virtex-II at 800MHz.
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