Hi group, When I am developing code for a hobby project, I find that XILINX webpack infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to remove it to pack more function into the XC95144XL target. I am using the version 6.1. Here is the sample code (complete and compiles) and the synthesized schematic is posted at . I think ADDR_NEXT can be connected to D only and HOST_DATA can be connected to pre-set/clr only. Any idea? Thanks.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity busmaster is Port ( ADDR: out std_logic_vector(7 downto 0); ADDR_CLK_I: in std_logic; ADDR_NEXT: in std_logic_vector(7 downto 0); HOST_DATA: in std_logic_vector(7 downto 0); HOST_CSWR: in std_logic ); end busmaster; architecture Behavioral of busmaster is begin ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I) begin -- process if HOST_CSWR = '0' then ADDR