Xilinx Webpack ISE and Verilog-2001?

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Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001?  If so, what
was the first version to support it?  I'm mainly looking at support for
'signed' number support.
(Signed regs, wires, inputs/outputs, and '>>>')



Re: Xilinx Webpack ISE and Verilog-2001?
Following link shows 2001 support on 5.1i ISE and later.

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html

This information is extracted from the ISE software manual guide.

http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm

Regards, Wei

===========================================================
Verilog 2001 Support in XST

XST now supports the following Verilog 2001 features. For details on
Verilog 2001, see Verilog-2001: A Guide to the New Features by Stuart
Sutherland, or IEEE Standard Verilog Hardware Description Language
manual, (IEEE Standard 1364-2001).

     * Combined port/data type declarations
     * ANSI-style port lists
     * Module parameter port lists
     * ANSI C style task/function declarations
     * Comma separated sensitivity list
     * Combinatorial logic sensitivity
     * Default nets with continuous assigns
     * Disable default net declarations
     * Arrays of net data types
     * Signed reg, net, and port declarations
     * Signed based integer numbers
     * Signed arithmetic expressions
     * Arithmetic shift operators
     * Automatic width extension past 32 bits
     * Power operator
     * n sized parameters
     * Explicit in-line parameter passing
     * Fixed local parameters
     * Enhanced conditional compilation
     * File and line compiler directives
=============================================================

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