Hi,
Does anyone know the frequency of the internal oscillator of Xilinx VirtexE FPGAs which is used to generate the CCLK for Master-Serial configuration mode? I'm aware that the datasheet specifies 4 MHz as default CCLK frequency but that isn't necessarily identical to the frequency of the oscillator.
What's the behavior of this oscillator after configuration? Is it turned off or can it be disabled through some option in the bit file?
Regards
Stefan Tillich