Hi,
We are seeing evidence that a DCM is intermittently selecting the wrong tap position after it completes its lock sequence after a DCM reset pulse. I'd like to know if anyone has experienced this effect, and if they were able to resolve this problem.
In a 2v6000, I am using a variable phase shift DCM which is driven by a 622 MHz clock (divide-by-2 mode). The DCM generates 311 MHz clocks on its clk0/clk180 output pins. This interface uses IOB DDR regs for a
622 Mhz/16-bit LVDS transmission solution.The DCM initial value is set to 0. After a DCM reset, the DCM is phase shifted to its predetermined optimal "error-free" setting. However, intermittently, the interface experiences a small amount of bit errors.
To eliminate the errors, the DCM is further phase shifted in one direction until it actually achieves error-free operation. The subsequent error-free window of operation in this mode matches very closely to the original calibration error-free window.
It is as if the DCM locking sequence is corrupted somehow, resulting in a mis-aligned tap position. We don't have conclusive evidence because we can't see inside the DCM to see its tap position. We have found that we can eliminate this error condition by applying another one or two reset pulses to the DCM.
I realize that voltage fluctuations and switching noise could be causing this effect. Nonetheless, I'd like to hear from real world experiences.
Thank you. John