I am registering a data bus at the input of a Xilinx Virtex FPGA (XCV300) using IOB registers. It appears that some of the register bits are locking in incorrect data.
All registered bits are brought back out of the device for debug purposes. When looking at logic analyzer waveforms, it appears that the data bus coming in is stable, yet a few bits inside the FPGA are registered incorrectly. We have tried to adjust the signal level of the logic analyzer to look for glitches on the input data bus but do not find any.
All we can figure is that there must be some ringing or transmission line effects on the data bus. Are the Xilinx IOB registers particularly sensitive to noise? What other effects could lead to registering the incorrect value? It appears that the setup time for the data bus is approximately 7.5 ns, so that is much greater than the Xilinx spec of 2.1 ns setup.
ANy thoughts would be appreciated.