Hi, I've tried to understand exactly which clocks a DCM will phase align when I do external or internal feedback by the book. I've read every bit of documentation I could find, but came out empty-handed. So maybe someone out there can help me out... This is the structure I have for internal feedback: module int_fb(clki, clko); input clki; output clko; wire clki_buf, clk_fb, clk_2x; assign clko = clk_fb; IBUFG ibufg0(.I(clki), .o(clki_buf)); DCM dcm0(.CLKIN(clki_buf), .CLKFB(clk_fb), .CLK2X(clk_2x)); BUFG bufg0(.I(clk_2x), .O(clk_fb)); endmodule Which wires are phase-aligned clocks here? External feedback: module ext_fb(clki, clkfb, clko); input clki, clkfb; output clko; wire clki_buf, clk2x, clkfb_buf; IBUFG ibufg0(.I(clki), .O(clki_buf)); IBUFG ibufg1(.I(clkfb), .O(clkfb_buf)); DCM dcm0(.CLKIN(clki_buf), .CLKFB(clkfb_buf), .CLK2X(clk2x)); OBUF obuf0(.I(clk2x), .O(clko)); endmodule clko is connected to clkfb outside the FPGA. I've omitted reset and locks for simplicity. Again, which wires are phase-aligned clocks here? Also related: what does the DESKEW_ADJUST attribute do? The documentation I found says only how you set it, but not what it does... Thanks, Gernot
- posted
20 years ago