Xilinx Virtex-4 RAMB16

Hello group,

I have used the new ISE 8.i simulator (nice propeller) to simulate a 9 bit read-only-memory using a BRAM16 primitive. The code is shown below. A number of new questions arise:

1) Is the code around the "begin" keyword, which maps the inputs to the primitive RAMB16 (BRAM or Block RAM) acceptable or is there a more concise/better method?

2) I initially went to the V4 library guide and found this primitive. I did not see there the RAMB_Sx_Sy primitives of Spartan yore, which lead me to believe that they are abandoned in Virtex-4. The Xilinx Virtex-4 User Guide ( ug070.pdf ) page 133 would lead one to believe that they are available. What is the story here?

3) Generally, I would like to transport my future designs between Spartan3s and Virtex-4 effortlessly. Are their any tips, ap notes, or other information out there on how to do this?

4) The INIT_xx => sytax is clumsy. Especially if I choose to use the ninth bit. What alternatives do I have?

5) I have been searching Google for code examples with the words RAMB16 and std_logic. Is there any primitive or keyword specific to Virtex-4 that would further refine my search?

6) I did not see the INIT value on the ISE 8.1 simulation which I expect to see at time 0. Is this a glitch in the 8.1 simulator?

Regards,

Brad Smallridge aivision dot com

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity bram9p is port ( clkb : IN std_logic; enb : IN std_logic; ssrb : IN std_logic; regceb : IN std_logic; addrb : IN std_logic_VECTOR(11 downto 0); web : IN std_logic; doutb : OUT std_logic_VECTOR( 8 downto 0) ); end bram9p;

architecture Behavioral of bram9p is

signal addrb15 : std_logic_vector(14 downto 0); signal dob32 : std_logic_vector(31 downto 0); signal dopb4 : std_logic_vector( 3 downto 0); signal web4 : std_logic_vector( 3 downto 0);

begin

addrb15(14 downto 3) "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36 SIM_COLLISION_CHECK => "NONE", -- "ALL","WARNING_ONLY","GENERATE_X_ONLY,"NONE SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion SRVAL_B => X"000000002", -- Port B ouput value upon SSR assertion WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_WIDTH_A => 9, -- 1,2,4,9,18 or 36 WRITE_WIDTH_B => 9, -- 1,2,4,9,18 or 36 -- The following INIT_xx declarations specify the initial contents of the RAM INIT_00 =>

X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100", INIT_01 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F =>

X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INITP_xx are for the parity bits INITP_00 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 =>

X"0000000000000000000000000000000000000000000000000000000000000000") port map ( CASCADEOUTA => open, -- 1-bit cascade output CASCADEOUTB => open, -- 1-bit cascade output DOA => open, -- 32-bit A port Data Output DOB => dob32, -- 32-bit B port Data Output DOPA => open, -- 4-bit A port Parity Output DOPB => dopb4, -- 4-bit B port Parity Output ADDRA => (others=>'0'), -- 15-bit A port Address Input ADDRB => addrb15, -- 15-bit B port Address Input CASCADEINA => '0', -- 1-bit cascade A input CASCADEINB => '0', -- 1-bit cascade B input CLKA => '0', -- Port A Clock CLKB => clkb, -- Port B Clock DIA => (others=>'0'), -- 32-bit A port Data Input DIB => (others=>'0'), -- 32-bit B port Data Input DIPA => (others=>'0'), -- 4-bit A port parity Input DIPB => (others=>'0'), -- 4-bit B port parity Input ENA => '0', -- 1-bit A port Enable Input ENB => enb, -- 1-bit B port Enable Input REGCEA => '0', -- 1-bit A port register enable input REGCEB => regceb, -- 1-bit B port register enable input SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input SSRB => ssrb, -- 1-bit B port Synchronous Set/Reset Input WEA => "0000", -- 4-bit A port Write Enable Input WEB => web4 ); -- 4-bit B port Write Enable Input

end Behavioral;

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