Xilinx Virtex 4 device technology

Does anybody happen to know the if Xilinx Virex 4 and/or the QPRO familiy of devices are fabricated using the fully depleted SOI (FD SOI) technology as opposed to the traditional bulk CMOS?

Thanks,

Amr Ahmadain

Reply to
Amora
Loading thread data ...

Amora,

We do not use SOI in any of our products.

Aust> Does anybody happen to know the if Xilinx Virex 4 and/or the QPRO

Reply to
austin

Austin,

Thanks for your reply. But does that mean there isn't at least any consideration to use the SOI technology in the near future in building your devices? I think they do offer intrinsic performance and low-power edge compared to bulk CMOS.

Thanks again.!

Amr

Reply to
Amr Ahmadain

Amr, within a company like Xilinx, there are hundreds of ongoing considerations and investigations and plans about hundreds of possibilities. This newsgroup is a public forum, and you should not expect us to describe all our planned and not planned developments. Austin and I are reasonably candid, but we also have an obligation to keep future plans under wraps. This is a competitive field... Peter Alfke

Reply to
Peter Alfke

Peter & Austin,

I deeply apologize for not being of aware of these issues. My intentions were good.

Really sorry.

Amr

Reply to
Amr Ahmadain

Peter and Austin,

Again, please do accept my apologies. I asked this question just out of curiosity and maybe out of naiveness !!

Amr

Reply to
Amr Ahmadain

Amr, do not feel bad. No need to apoligize. Austin and I are able to decide what we want to tell the public, and what is better left un-said. Keep asking questions, and even complaining (hopefully not too much). We will answer to the best of our ability, but also in loyalty to our employer. Cheers Peter Alfke

Reply to
Peter Alfke

Peter,

Thanks a million for the reply. This is really what I needed to hear from you.

I can tell you for sure, I'll keep asking scores of questions, but complaining a little:)

Amr

Reply to
Amr Ahmadain

Amr,

No apology necessary.

Some further notes on SOI (that I can share):

In order to remove or minimize the variation in timing in SOI from the floating wells, one needs to add taps. The addition of the taps to every well, results in the area increasing dramatically. That makes the FPGA cost too much, hence the process is not commercially viable. This has been one of the reasons for its non-use.

SOI is also heralded as being more robust for atmospheric neutrons. But it is only twice to five times better than bulk substrates. A factor of two to five is not considered good enough to warrant its use.

SOI also does little to increase the LET for heavy ion strikes, unless the design has a lot of taps to collect charge (which adds area again).

Xilinx pioneered a major process development with the introduction of triple oxide (now running in two completely different fab lines: UMC and Toshiba). This allowed us to reduce the leakage current of our devices substantially, as well as provide an almost two times better SEU time to upset (over the previous generation technology, or other 90nm FPGA competition).

We do consider process techology where it can provide the most benefit. In this case, SOI would increase area, not do anything for leakage, and cause all kinds of other problems. Triple oxide solves a number of known problems, by using masks and steps that are standard to the semi industry.

Aust> Peter and Austin,

Reply to
Austin Lesea

Austin Lesea schrieb:

Also, without knowing as much detauls as austin, I suspect that in a design as heavily dominated by interconnect as an FPGA the area increase results in longer wires which increases capacitance and therefore power consumption and delay. This mitigates the two main advantages of SOI.

Kolja Sulimma

Reply to
Kolja Sulimma

Kolja,

You are correct. The capacitance of the interconnect certainly dominates as far as speed is concerned (over any advantage of a faster transistor in SOI).

What is also interesting, is if you reduce the capacitance by 10% (ie using lo-K), the speed only goes up by 5%. Thus, the effect of lowering the K can actually be offset by pushing the transistor process in the fabs to get all the speed back again (as a 5% faster transistor is easy to do).

That is why we are neither for, nor against lo-K. For us, it just doesn't matter! Toshiba uses lo-K. UMC does not (for V4). The processes are adjusted for equivalent performance. And, there is hardly any difference in dynamic power after all is said and done (one datasheet covers both fabs).

Probably the biggest process technology improvement in V4 was the use of triple oxide: the thick mid-ox device used for memory resulted in much less static current, and also in superior SEU resistance to upset. Regular use of 90nm 6T cells for memory means that the probability of upset is worse than it was in 130nm. It also provided excellent speed performance and low leakage for the pass-gates.

Additionally, the lifetime of the FPGA remains at 20 years, when Intel is quoting a 7 year life for their 90nm processors. By using all 90nm transistors, the reliability is compromised, as we are beginning to see "wear out" effects for the technologies below 90nm. By keeping the memory cells and pass gates at a thicker oxide, we also are using far fewer 90nm transistors, and increasing the reliability of the hardware itself.

There are also substrate implantation techniques that can also be used for soft errors, which would cost far less that redesinging for SOI.

Austin

Kolja Sulimma wrote:

Reply to
Austin Lesea

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.