Xilinx VIIPro mixed configuration voltages

I'm using a VIIPro with Bank 4 Vcco set to 3.3V. The PROM is an XCF04S which has separate Vccint (must be 3.3V), Vccjtag and Vcco (can be 2.5 / 3.3V) connections. I'm a little confused as the FPGA has some configuration pins that are 2.5V (Vccaux) which apparently cannot be driven to 3.3V but in the datasheet it states that the configuration device Vcco and the FPGA Vcco need to be the same value. If I could use 2.5V I would but in this case it has to be 3.3V.

I might have figured this out OK but the datasheet information on the PROM and FPGA seem to contradict in some places. Does anyone have any experience of doing this and any advice that would be useful?

So far I've put a 4K7 pull-up to 3.3V on the OE/Reset to Init_B line, a 4K7 pull-up to 2.5V on the CF to ProgB line and a 4K7 pull-up to 2.5V on the nCE to DONE line. On the PROM all Vccs are 3.3V. A screenshot of the diagram is available at the link:

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if interested.

TIA for any help.

Rog.

Reply to
Roger
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Given your are using the Platform Flash you are probably using slave serial mode programming. CCLK will be driven by the V2-Pro so what you need to be careful of is the data input voltage levels. Usually I wire the relevant bank voltage Vcco to the Platform Flash to solve this issue. Usually the DIN goes in on bank4 or 5 but check that for your given device.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board.

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Reply to
John Adair

Actually, the FPGA outputs the CCLK in Master Serial mode, which is what the OP is using (M2=M1=M0=GND)

(FYI in slave serial, the CCLK comes from a source external to the FPGA)

=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for

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Philip Freidin

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