Xilinx, VHDL, Verilog, ModelSim, BMP

You are absolutely right. My first posting was to show how to get around the problem that some simulators (e.g. Modelsim) cannot write out the NULL byte. Of course a more general solution is using $fseek(fd, -3, 1) as you pointed out.

I know NCVerilog can do this, but not all simulators work this way.

Jim

Reply to
Jim Wu
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Hi,

I ended up with the following, which works:

Are you saying that a more concise way to do this would be with a relative seek? I don't have a good reference for these system tasks, the best I could come up with is what I put above, based on reading some web material. But this:

Seems much more concise... It's equivalent? Eric

Reply to
Eric Crabill

NC-Verilog didn't work this way originally either. We added this capability in response to user requests. Perhaps other simulator vendors would also be willong to do this if they got enough requests.

In the meantime, the basic workaround you suggested should work.

Reply to
Steven Sharp

What you came up with should work. It even has the advantage of being clearer in some ways, and doesn't rely on the implementation correctly following the LRM in writing out 32-bit chunks with %u. But a relative seek is more concise. The third argument to $fseek is 0 for a seek relative to the start of the file, 1 for a seek relative to the current position in the file, and 2 for a seek relative to the end of the file. This assumes that your simulator has implemented $fseek correctly, of course.

Should be.

Reply to
Steven Sharp

Hi,

Sorry it took so long, but here it is, a module that will record RGB video data to TIFF files. A small testbench is also provided:

formatting link

I hope it helps somebody, I found it useful. I'd like to thank everyone for their input on this topic.

Eric

Reply to
Eric Crabill

i want to make a project in verilog plze guide m

-- ibadwww.totallychips.com - VHDL, Verilog & General Hardware Design discussion Foru

Reply to
ibad

i want to make a project in verilog plze guide m

-- ibadwww.totallychips.com - VHDL, Verilog & General Hardware Design discussion Foru

Reply to
ibad

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