xilinx v5 ddr2 controller

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I have used the core generator for a DDR2 controller and I'm trying to
implement my own user application. In my current simulation the
controller comes out of calibration but when I try to write to memory
the debug output tells me that the data are all X but the user
interface waveforms look reasonable. I'm sure I'll find what the
problem is in due time but I'm wondering if anyone who walked through
this path has any suggestions.
Also this is with the Xilinx memory model. I tried a Micron specific
memory model I downloaded separately
(http://www.freemodelfoundry.com/fmf_vlog_models/ram/mt47h64m16.v ) but
this one seems to be extremely sensitive to clock frequency and keeps
complaining about input clock frequency not being stable even though
the changes are only a couple pico seconds every clock. Anyone has
experience with this model?


Re: xilinx v5 ddr2 controller
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I'm not sure what you mean by core generator DDR2 controller, but
if you're talking about MIG, then I have successfully used this
with the Micron memory models available on the micron website.

Re: xilinx v5 ddr2 controller
Hi Muzaffer,

I more or less know what you are going through, having spent time
debugging the VHDL version of the FMF DDR2 models (on a side note, I
posted my particular situation in their forums, but no one there seems
interested in discussing it).  Overall, the models are great, but I've
just found a few minor problems here and there.  One such problem,
maybe similar to yours, was that the PLL used to generate the memclk
did not provide a duty cycle of exactly 50%.  Because of this, there
were some clock signals with inertial delays in the FMF model that
never fully propagated; consequently I had clock signals that did not
oscillate.  The fix required adding the keyword 'transport' to the
statement, and disco (AFAIK, this did not disturb any other

Anyway, I have had success using MIG V5 DDR2 controllers with the FMF
DDR2 VHDL models, but like Gabor said, since you're in a verilog
environment and micron offers verilog simulation models of their
components, I'd use them.

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