Hi All,
Let say I have one bank in V4 device with all single ended outputs and one differential output. I'd like to have VCCO =3.3V.
This is not allowed in V4, because obufds_33 doesn't exist in V4 and PAR ends with error.
What going to happen if I'll declare all outputs in this bank as LVCMOS_25 and LVDS_25, but physically connect VCCO to 3.3V on board?
Will it damage the device?
Probably I'll get some out-of-spec voltage levels for LVDS output. But it's fine for me.
My situation is that diff output CLK signal was overlooked on the board and placed in the 3.3V bank. Board can work with single ended CLK signal but it's better to have differential.
Thanks