Hi *,
I use several DCMs in my V2P7-design, and have the following problem:
After the FPGA is configured, the input clock is outside of DCM specs (it's somewhere in the 1MHz-range). Of course, the DCMs can't achieve a lock with this. Awhile later (the exact time is unknown) the input clock is switched to 25MHz. In order for the DCMs to lock, I then have to issue an external reset.
What I'd like is some way to do this automatically. Normally, I'd use the status(1)-bit from the DCM, which should indicate the input clock was lost while changing. But this bit is obviously only set when a lock was achieved before and the clock is lost after that. If the DCM never locks in the first place, the status-bit is never set.
The main problem here is that I don't know exactly when the input clock will be changing, i.e. when I have to issue the reset.
Any ideas? Is there some clever way to do this I'm not seeing?
cu, Sean