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Xilinx V2-Pro + Select Map programming

I've got a design using Select Map mode to program a Xilinx V2-Pro part. Many of the boards work, but one has stopped accepting the bit file download. Everything seems to proceed properly, but the DONE signal is never asserted. I can download via JTAG to the part just fine, but it just won't accept the Select Map download.

When my code asserts the PGM pin, DONE goes away and INIT is asserted. After a bit, I release PGM, then INIT goes away. All correct so far. I send down the data, but DONE is not asserted at the end.

All voltage levels look OK, timing looks fine, plenty of setup/hold time on the data going into the V2-Pro. This board used to work, but at some point decided to be a problem.

Also - if I load the FPGA via JTAG, I can run a set of diagnostics using the same 8 bit data bus and the diagnostics pass, ie, my data bus looks to be properly connected.

As far as I can tell, the FPGA appears to work perfectly EXCEPT it doesn't like to be downloaded via Select Map.

Has anyone else seen problems like this? Is it likely that the FPGA couls be damaged such that it can't accept download data but that the same data pins work fine after the part is programmed via JTAG?

The exact same .bit files work fine on other boards.

Suggestions?

Thanks!

John P

Reply to
johnp
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"johnp" wrote in news:1112744398.572710.3530 @z14g2000cwz.googlegroups.com:

Is INIT pulled low at the end?

Are the CS, WR and CCLK signals correct during downloading? Are the mode pins set correctly? (These are all inputs and would not be tested by your bus diagnostic.)

--
----------------------------------------------------------------
Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com
Reply to
Dave Vanden Bout

Howdy John,

You may have already tried this, but the first thing that jumps to my mind is the problem I had a few years ago: make sure you toggle CCLK a number of times *AFTER* DONE goes high. Turns out DONE means "you're almost DONE," or "clock CCLK several more times, then you'll be DONE,", or maybe "you just thought you were DONE." :-) Unreliable things can happen if CCLK isn't toggled several more times.

Good luck!

Marc

Reply to
Marc Randolph

Mark & Dave -

1) INIT is not pulled low at the end - it does not indicate any error. It *does* wiggle as expected at the start of the programming sequence.

2) CS is pulled low, the WR signal is attached to a control signal and appears to be acting properly.

3) CCLK appears (using a scope) to be fine. D[7:0] show ample setup and hold time to BOTH edges of the clock.

4) I've tried sending extra 0xFF bytes at the end of the .bit stream, it doesn't help. I've also tried at the start of the stream.

I'll keep debugging and let people know wht I find.

I wonder if it's reasonably possible for an FPGA to die in a manner where JTAG download works, normal operation works, but Select Map download fails.

Thanks for the help, I'll keep pulling my hair out.

John P

Reply to
johnp

"johnp" wrote in news:1112800047.283747.285480 @f14g2000cwb.googlegroups.com:

Sure. A failure on the CS, WR or CCLK inputs would account for what you are seeing. Can you inspect these connections on the FPGA, or is it a BGA package?

You can create a design that outputs signals on CS and WR. That will prove they are not burnt and are connected to the PCB.

If you place a static value on the data lines and toggle CCLK for a while, then INIT should go low because of a CRC error. That would prove CCLK is working.

Can you configure the FPGA in slave-serial mode? Then your download only depends on the CCLK and D0 inputs. If that works, then most of the configuration circuitry in the FPGA is OK

--
----------------------------------------------------------------
Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com
Reply to
Dave Vanden Bout

Dave -

I think the CCLK pin is either open or blown out. I changed the FPGA to be Master Serial mode, lifted the CCLK pin at my driver, and powered up. No sign of the FPGA producing a CCLK. Unfortunately, the FPGA is in a BGA package, so I can't examine the pin. I think this expereiment shows either a floating or blown out CCLK pin on the FPGA. :(

Thanks for your help.

John P

Reply to
johnp

BGAs are like women -- you can't live with them and you can't live without them. IMHO.

Bob

Reply to
Bob

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