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Xilinx tools, bugs all around?

Hi

is it only me that every time I try to use some a little advance feature I trap into some Xilinx bug??

1) implementing SRL16 based serial divider, found bug in MAP 2) implementing JTAG Hub found synthesis bug 3) implementing frequency meter in FPGA found P&R bug with Virtex 4 devices

for 1 and 2 there are simple workarounds those are not fatal.

but with the Virtex 4 bug, thats a bit scarier

a simple design with 16 counters connected to 16 pin locked GCK inputs.

P&R fails, saing one signal is not fully routed

the same desing with 16 clocks works Ok for Virtex-2 !!! Virtex 4 has more clocks but what does it help if the tools are broken???

I am about to start a VERY challenging designs that will be housed in several ATCA racks, so far considering V4FX20 as the main FPGA on the boards, but if the V4 support has more issues that we will find too late, than maybe its not to late to reconsider the design to use V2Pro what hopefully has less bugs as it has been in use for longer time.

Antti

Reply to
Antti Lukats
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Hi Antti, Make sure you open a webcase thingy. I want that stuff fixed when I get around to using those parts!! Seriously, I'd stick with the newer part. You'll find you get better support from Xilinx than on the older parts. Remember, they're trying hard to flog these new devices to their biggest customers who won't be happy with problems like the one you describe. And it looks better on the CV. Cheers, Syms.

Reply to
Symon

Hello Antti,

If PAR only fails to route a single signal, that's usually an indication of a packing or placement problem leading to an unroutable connection, rather than a congestion issue. These problems are usually not too difficult to understand and correct with packing or placement constraints. Although you are focused on the number of clocks in the design, you don't say whether the unrouted signal is a clock net or something else, so I won't speculate on the root cause.

I suggest examining the design in FPGA Editor and trying to understand where the routing conflict is. If you are unable to make any progress with this method, I suggest opening a webcase and providing a test for investigation.

Regards, Bret Wade Xilinx Product Applications

Reply to
Bret Wade

Which version of ISE? I trust you are reporting these bugs to Xilinx (open a webcase) so that they get fixed before I migrate to 7.1 (still using 6.3)

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--Ray Andraka, P.E.
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Reply to
Ray Andraka

Hm, thanks for some hints, but well I think there is a an issue related to V4 because the same design with 16 clock routes OK on V2 without any problems. the all design occupies less than 4% of the V4, so I am pretty confident the design is routable. And if simple design is routable there should be no reason to look into FPGA editor or add placement constraints to make the design routable.

I will try to open a webcase too.

Antti

Reply to
Antti Lukats

Hello Antti,

Yes, this is likely a tool problem related to a new feature in the V4 parts such as the Regional Clocks. But until we know more details about the problem, like which connection is unrouted, we are no closer to a solution.

It would also help to know what tool version is involved. I suspect that you are not yet using 7.1i since I would expect a different failure mode. 7.1i does an "unroutability check" before routing that detects and and errors out on unroutable connections, but you didn't describe that scenario. The 7.1i version also solves many of the early teething problems found with V4 devices.

Regards, Bret

Reply to
Bret Wade

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