Hi all,
I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set up viloations). What are the steps to be taken to meet the frequency other than doing a pipeline in RTL. I am using Xilinx FPGA's.
regards
Prav, The approach is very dependent of the root cause. you have to investigate where your time budget is spent, logic or routing if is on logic try to reduce the number of logic levels, pipeline, re-balance registers, etc. if is on routing try to floor plan, use area constraints, different switches in map/par etc.
Aurash
prav wrote:
If you try to perform something too "complex" in your 8 ns, you have to change the complexity. Often the problem is that logic has a larger number of logic levels than the application requires. Find the critical path, figure out if you need 12 levels of logic - if there's another way to produce the same result in fewer logic levels, do it. Often the FPGA you target has advanced silicon features that can speed up the implementation if you know it's there and can code to use it. Pipelining is often the best approach, registering parts of the slow path in the previos cycle.
I can't make a baby in 4.5 months. Is there a way to meet my deadline without using two women?
of course it is, just make a baby with each, and we can find a marketing guy to say that you have 2 childrens in 9 months equals to 4.5 months on average / baby Aurash
-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Hi austin,
Generally what is the budget we give for Logic and Rout> Prav,
Prav, the budget is your clock period minus setup and hold (assuming SDR)
Aurash
-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Hi Aurelian ,
What do you mean by re-balance registers??
Regards, Prav
Aurelian Lazarut wrote:
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