Xilinx Timing Constraints for Asynchronous Logic (asynch latches)

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I'm trying to implement an ISE 5.2.03i XST verilog dual-rail adder
core (generated from Balsa) on an XCV2000E-bg560-6 that is included in
an EDIF (generated by HandelC) design flow. A post-translate
simulation of the core indicates successful reset and valid then empty
inputs are applied. However, evil red lines/Xs occur waiting for
indication that the add has completed.

Behavioural simulation of the core, and behavoural cosimulation of
handelc+core are fine

The core is delay insensitive, but I must still (obviously) meet setup
and hold constraints. Could anyone point me to an example/tutorial or
give me instructions on how to apply xilinx timing constraints when
dealing with LD and LDC latches driven by asynchronous signals.

Sorry if this is a stupid question, I did try to find this on the
support site and RTFMed but there was no clear answer.


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