1. Home
  2. Field-Programmable Gate Arrays
  3. Xilinx timing constraint problem

Xilinx timing constraint problem

Dear all,

I place a timing constraint on a pair of registers (from, to) either side of some logic. After I run the ISE 6.3 toolchain, I look at the actual delays for the constraint in Timing Analyzer.

The constraint seems to have been applied from the source register which I specified as my destination, to a register or pad elsewhere in the design. The constraint is applied to logic other than specified.

Any suggestions?

Cheers,

Dave.

Reply to
Dave Roberts
Loading thread data ...

Can you check the PCF to see if the FROM TO still references the correct register pair?

Russ

Reply to
Russ Panneton

Yes - FROM, TO is correct. The constraints are still being applied incorrectly FROM my specified TO group, going to some arbitrary destination. Not sure what's up.

Thanks,

Dave.

Reply to
Dave Roberts

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.