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Xilinx Tight packing : Map error, the tools don't get it ...

Hello,

I'm trying to pack something into two SLICEs and the tools don't get it ... I get map error. And it should be possible to do what I want since I can "draw" it in the FPGA editor. (I'm using ISE7.1 sp4 and I target spartan 3)

What I'm trying to pack a a dualport distributedram (RAM16X1D) and a 5:1 mux in two slicesM, one above the other.

On the first slice (top one) is the classic RAM16x1D stuff. On this same slice, I want to place a F5Mux between the two output of the DRAM, commanded by BX (actually, BX will be forced to 1, I just want the second output of the distributed ram on the F5 output pin).

On the second slice (bottom one), I get a 4:1 mux done with the two LUTs

  • the F5 on the slice. And on the same slice, I want to use the FX mux to mux between either the output of the F5 of this slice, or the F5 out pin of the slice above.

The VHDL code I write as test is givent at the end of the post and also available there :

formatting link

The error I get :

--
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=reg,
RLOC=X0Y1)
   which require the combination of the following symbols into a single
SLICEM
   component:
   	RAMDP symbol "memcell_I" (Output Signal = dob_i)
   	MUXF5 symbol "f5_I" (Output Signal = fxb)
   The function generator memcell_I is unable to be placed in the G position
   because the output signal doesn't match other symbols' use of the G
signal.
   The signal dob_i already uses G.  Please correct the design constraints
   accordingly.
Reply to
Sylvain Munaut
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Hi Sylvain, Does it help to use the floorplanner after translate?

So, remove your RLOCs from the code. Run Translate. Run the floorplanner. Place the parts on the floorplan. Export a UCF file? Just a thought. Good luck, Syms.

Reply to
Symon

Nope, the floorplanner don't let me put the memcell in the same couple of slice as the F6 mux contruct.

I'm investigating how to create a hardmacro now, see if that would work.

Sylvain

Reply to
Sylvain Munaut

I couldn't find my notes quickly so I'll just ask the question:

Are you certain that the dob_i and doa_i signals from the dual-port CLB SelectRAM - DPO and SPO, respectively - are on the correct pins (I1/I0) for the MUXF5? You could just try swapping I1/I0 for a quick check to see if the orientation is inverted from what you expect.

Reply to
John_H

No I'm not sure it's correct in the version I gave (I think so though), but I did try different swapping of the pins for the MUXF5 and MUXF6, none worked.

Sylvain

Reply to
Sylvain Munaut

Sylvain, try again (hope you haven't started writing a lot of scripts yet). The code below packs correctly into two slices without the location constraint and init attributes (even using 6.3.03i), I'd be surprised if adding them makes it fail to pack. I think John_H gave you good advice. It did take me an hour to work out correctly... now I can get to today's Sudoku puzzle...

Regards, Just John

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components. library UNISIM; use UNISIM.VComponents.all;

entity Sylvains_poser is Port ( clk : in std_logic; we : in std_logic; di : in std_logic; addr_a : in std_logic_vector( 3 downto 0 ); addr_b : in std_logic_vector( 3 downto 0 ); imm : in std_logic_vector( 3 downto 0 ); sel_imm : in std_logic_vector( 1 downto 0 ); sel_ab : in std_logic; sel_rm : in std_logic; dout : out std_logic; dout_a : out std_logic; dout_b : out std_logic ); end Sylvains_poser;

architecture Behavioral of Sylvains_poser is signal doa : std_logic; signal dob : std_logic; signal mux_ram : std_logic; signal mux_imm : std_logic; signal out_sel : std_logic_vector( 1 downto 0 ); signal dp_16x1 : std_logic_vector( 0 to 15 ) := x"1234"; begin

-- process( clk )

-- begin

-- if RISING_EDGE( clk ) then

-- if we = '1' then

-- dp_16x1( conv_integer( UNSIGNED( addr_b ))) addr_b(2), A3 => addr_b(3), D => di, DPRA0 => addr_a(0), DPRA1 => addr_a(1), DPRA2 => addr_a(2), DPRA3 => addr_a(3), WCLK => clk, WE => we ); with sel_imm select mux_imm mux_ram, I0 => dob, I1 => doa, S => sel_ab); Mux_RM : MUXF6 port map ( O => dout, I0 => mux_ram, I1 => mux_imm, S => sel_rm); end Behavioral;

Reply to
JustJohn

THANK YOU !

Damn you're right, I must have missed that particular mux config, I probably tried one combination two times ...

I already made a hardmacro test but I like the HDL better ;) especially since you apparently can't "configure" a hardmacro, I would have had to do 16 differents hardmacro cells ...

Well, the tools did get it after all, it was me who failed ;)

Sylvain

Reply to
Sylvain Munaut

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