Xilinx SystemACE on multi-FPGA board

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OK, Xilinx was uniquely unhelpful this time, so I resort to this
list. My setup is a SystemACE connected to 1 or 2 Virtex2 FPGAs,
and also to a PPC405GPr running Linux. The second FPGA is optional,
and when the optional FPGA is installed, the JTAG is rerouted through
and a different ACE file supplied. The CF card contains a second
partition where the Linux fs (ext3) lives.

My problem is that when the second fpga is installed, the board
will crash Linux within a few minutes. The SystemACE driver is
getting an error that the JTAG configurator was unable to read
the configuration stream from the CF. (This is 1/2 nonsense, because
the chips were programed by the SystemACE under the watchful eye
of u-boot before Linux was even started.)

The second FPGA is getting programmed (during u-boot) because the
PPC is able to discover it's PCI id at boot time.

The CFGADDR[2:0] bits are unconnected on our board, as are the
CFGMODEPIN, POR_BYPASS and POR_RESET. The CFGPROG goes to both
FPGA devices (with a single pullup.) The CFGINIT is connected to
only the first FPGA.

So does anybody have any clue why in blue blazes the SystemACE is
going nuts when the second FPGA is installed?
- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Re: Xilinx SystemACE on multi-FPGA board
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Not enough information on your problem.

1) In the single Virtex-II case, what does the complete JTAG chain look like?
2) In the dual Virtex-II case, what does the complete JTAG chain look like?
3) Have your connected the DONE pins of the Virtex-II devices together?
4) In the dual Virtex-II case, do both device go DONE?
5) Which device is connected to the MPU port of the SystemACE device?
6) What holds the PPC405GPr in reset until both Virtex-II devices have been
configured?
7) What exactly is a PPC405GPr, I think that this is discrete PPC405, but which
one?
8) What exactly does this mean?
       "The SystemACE driver is getting an error that the JTAG configurator
        was unable to read the configuration stream from the CF."
9) It sounds like you filed a case with our hotline, what number were you
assigned?

Ed McGettigan
--
Xilinx Inc.

Re: Xilinx SystemACE on multi-FPGA board
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Ed McGettigan wrote:

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ACE.TDO --> FPGA1.TDI
FPGA1.TDO --> ACE.TDI

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ACE.TDO --> FPGA1.TDI
FPGA1.TDO --> FPGA2.TDI
FPGA2.TDO --> ACE.TDI

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Yes. The Init lines are also connected together and to the SystemACE.
I thought at first that they were not, but I was mistaken.

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Yes, although my test for that is to note that them both respond on
the PCI bus, and seem to function properly. Also, I note that I get
the CFGDONE bit in the STATUSREG before I continue from u-boot.
Oh, and they are Virtex-4, not Virtex-II. Although we have a V-II
variant of the board as well.

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The PPC405GPr, through CS1#.

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Nothing, the U-Boot bootstrap loader polls for the CFGDONE bit before
u-boot is allowed to proceed with reading the kernel from the FAT FS.

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It is an IBM PowerPC405GPr. Part number IBM25PPC405GPR3BB333. We
do not use any internal 405 cores, we use a discrete part that has
PCI, SDRAM controllers, etc. The PCI bus of the PPC connects to
the FPGA[s], so the FPGA devices show up as PCI devices to Linux.


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These are the error, status and control register contents when the
Linux kernel discovers the error:
  CONTROLREG=0x10a STATUSREG=0x19035e ERRORREG=0x2098

The Linux kernel is 2.4.33-pre1 w/ the mvista SystemACE drivers
for Linux 2.4.

The error messages from the kernel driver are:
CompactFlash write command failed
CompactFlash sector failed to ready
CompactFlash sector ID not found
JTAG controller couldn't read configuration from the CompactFlash


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Case # 628407
(The webcase person asked none of these questions.)

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Re: Xilinx SystemACE on multi-FPGA board
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I had a quick discussion with our Linux/UBoot expert and the SystemACE
designer as well as reading your original case that you filed with our
hotline and we believe that the SystemACE driver code that you are using
is resetting the SystemACE and causing another configuration of the
devices in the chain.

In the case of the single FPGA in the chain the SystemACE reconfiguration
may complete and return control to the MPU port before another MPU access
is made.  While in the case of the two FPGAs in the chain the reconfiguration
is still occurring when you attempt another MPU access.  In any case you
should not be reconfiguring the devices a second time (unless you really want to)
and our Hotline had given you instructions on how to prevent the reconfiguration.

If you would like to confirm this theory you can put a scope probe on the
CFG_TCK pin from SystemACE and you should see it actively toggle, stop for
a period of time after the 1st configuration and then restart again at some
point before stopping permanently.

 >> 9) It sounds like you filed a case with our hotline, what number were
 >> you assigned?
 >
 > Case # 628407
 > (The webcase person asked none of these questions.)Our

The hotline engineer assign to your case did not ask any of these questions
that I posed as your original query was very different from the one that
you posed here on comp.arch.fpga, but I do believe that they did give you
an answer that will resolve the problem when you implement it.

Ed McGettigan
--
Xilinx Inc.

Re: Xilinx SystemACE on multi-FPGA board
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Ed McGettigan wrote:
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(Thank you for actually *understanding* my situation! It's a relief.)

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If you are referring to the FORCECFGMODE and CFGMODE bits, note in
the CONTROLREG dump that they are set according to the recommendations
we received: FORCECFGMODE=1, CFGMODE=0, CFGSTART=0. I've put dumps of
the CONTROLREG in several places in the driver and I do not see that
those bits are being changed.

I agree that it seems like the SystemACE thinks it needs to reload
the FPGAs. The question is *why* does it think that. So far as I can
see, the FORCECFGMODE should prevent that. I can't find anywhere in
the Linux driver that this bit is being wiggled, and a dump at the
crash point shows that it is still set up correctly.


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I will try to perform this test.

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- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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