Xilinx System generator vs Simulink HDL Coder

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Hi all,
Anyone know the differences between Xilinx System Generator and
Simulink HDL Coder?
Thanks a lot.

Richie


Re: Xilinx System generator vs Simulink HDL Coder
snipped-for-privacy@gmail.com writes:

Quoted text here. Click to load it

About 10,000 UK pounds :-) Sysgen is fairly cheap, HDL coder is
expensive.

I've used sysgen, and you have to use a load of Xilinx blocks to do
everything.  Not having used it, I assume that HDL Coder is "standard"
Simulink blocks with bit widths on them, using the fixed-point toolbox
(which costs more money).

HTH!

Cheers,
Martin

--
snipped-for-privacy@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
We've slightly trimmed the long signature. Click to see the full one.
Re: Xilinx System generator vs Simulink HDL Coder
To all,
    I just happened to be at Mathworks today and was reading the help files
on the Filter HDL coder.  I have also been using the Xilinx Sysgen and
Simulink to try to model a filter I generated in the Xilinx Core Generator.
So far I'm not too happy with the Sysgen implementation and it's link to the
Modelsim simulator. I've had to jump through a lot of hoops just to get the
model of the filter to run and the model runs fairly slow. It also is
impossible to match what I get out of the filter in Simulink to what I get
when I simulate my VHDL/core directly from Modelsim/ISE.  I can not get the
Simulink model to run at more than a 1 MHz maximum clock rate. When I run it
at that rate what occurs in a few microseconds in the VHDL simulation take
milliseconds in Simulink time and it takes a long bit of real time to run
those few milliseconds of simulation. I'm currently taking a course on
Simulink but the support for the  Xilinx Blockset seems to be lacking.
Perhaps I'll be enlightened tomorrow but I'm having my doubts.
    I am interested in the VHDL coder simply because it produces a VHDL
module that looks like it is fairly easy to understand and should be easy to
instantiate and simulate. None of the clock rate issues etc. that seem like
a snakepit in the Simulink/SysGen method. I'm still keeping an open mind but
as the previous poster stated everything cost big bucks via Mathsoft. The
SysGen is fairly cheap but you also need the Signal Processing and
FixedPoint Blocksets and also the equivalent toolboxes to do anything
worthwhile, at least in my case. We are about to buy more licenses of
Matlab/Simulink and Xilinx tools so I have to make up my mind soon. It takes
awhile to evaluate these things and who has that much time?  I do like
working with the fixed point toolbox and blocksets because it makes it
easier to track the binary point of the data. I haven't done that much with
fixed point so maybe it just seems good because I'm a novice at it.  Most of
my designs are just moving data in and out in different formats/rates etc.
I'm trying to use FPGAs to do filtering but right now most of that is done
in floating point sw on Origin supercomputers.
    I'll read more on it tomorrow.

    My 2 cents.

CTW


Quoted text here. Click to load it



Site Timeline