Xilinx System Generator -> Block RAM

Could anybody explain me the algorithm of the generating RAM (ROM) modules by Xilinx System Generator?

I need approximately 16000 of the 12-bit words stored in high speed ROM. I consider that optimal decision is to use twelve 16k x 1-bit primitives with full pipelining. But SystemGenerator's ROM does not contain any optimization settings. It generates the strange architecture which used only 11 RAMB16 but extremely slow. The generated RAM contains eight not pipelined 9-bit RAMB16 with additional LUTs and registers and three pipelined 16k x 1bit.

Is there any workaround how to generate necessary ROM architecture (not manually)?

Xilinx System Generator version is 8.1.

PS The other strangeness is a latency of the generated ROM. When I set Latency=5 I see generic "latency => 4" in the generated ROM instantiation (in VHDL). But when I see generated .edn I don't see any additional registers. There are not pipelined RAMB16 + FDE (latency is

2) or pipelined RAMB (latency is 2 also).

PPS When I say "pipelined" I mean that property DOA_REG is set to (string "1") in generated .edn core. And when I say "not pipelined" I mean that property DOA_REG is set to (string "0") in the one.

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aphedorov
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