Xilinx gurus out there,
I have a very very simple design with a 24 bit counter, and I am using bit 24 in an always block like this
always @(posedge cnt[23])
Xilinx is telling me that it didnt automatically insert a clock buffer, and that it thinks this is a clock. I then added // synthesis attribute BUFFER_TYPE of cnt[23] is bufgp
to my verilog and to a .xcf file (that I specified as synthesis constraints file in synthesis properties).
However synthesis is still reporting that cnt[23] is a clock and the buffer type is NONE and that I need to specify buffer_type for if I want it to insert a buffer.
What am I doing wrong? Based on what I read about synthesis attributes, they can just go inline with the verilog, but it doenst seem to be getting picked up.
Any ideas?
Thanks,
-J