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Xilinx SRAM clock-to-out and input constraint with forwarded clock

Hi,

I have SRAM connected to a FPGA. The clock is forwarded to the SRAM by the FPGA (using ODDR trick). The input clock to the system is of another frequency and is internally multiplied by a DCM. Lets call the input clock (on the pad) clk_in and the internal DCM generated clock clk_1x

Now, I'd like to constraint :

- The clock to out from my internal clk_1x to pad for the various outputs - The skew between all the pins. (Since I use IOB registers, it should be constraint by design but I'd like at least a report ...) - The valid window for capturing the incoming signals.

And somehow I can't figure out how to do these because I don't have a "pad" that reflects my internal clock. If I just try to put an OFFSET relative to my clk_in, then it outputs mostly garbage because the clk_in and clk_1x have different frequencies and so it tries to consider intemediate edges and stuff but I don't care about that, all the design is clocked on clk_1x and not clk_in ...

I looked at the Xilinx example but couldn't find one that fits. Each time they have the external clock directly feed the internal logic and not a DCM modifying the frequency in the middle.

Cheers,

Sylvain

Reply to
Sylvain Munaut
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You can't. You must specify FF to PAD. The path between a flipflop and an output isn't covered by a clock domain.

TIMEGRP "all_ff" = ffs("*"); TIMEGRP "trigger_analog_pad" = pads("trigger_analog_out"); TIMESPEC "TStrigger_analog_out" = FROM "all_ff" TO "trigger_analog_pad" 7;

See above. The path between an input and a flipflip isn't covered by a clock domain.

You have to calculate this by hand.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
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Reply to
Nico Coesel

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