xilinx spi core question (microblaze)

anybody ever used the SPI core for microblaze? I found as example only a montevista spi driver which basically is doing all the bitbanging at a low level and uses it's own fifos, i.e. not using the xspi routines described in the xilinx_drivers reference. Are there any problems with the xilinx routines? Anybody some examples of usage? Taco

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taco
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Yes. I used it on a project last year to talk to a MxFE (Mixed signal front end) ASIC with a simple SPI interface. Not too tricky, but you do have to setup an interrupt handler. The example code is a pretty good start, and there is a dummy interrupt handler that you can copy/ modify that will do most of what you want. Unfortunately, I can't share the code as it is unpublished, but the core isn't too hard to work with. I don't believe the hardware supports FIFO's, though.

One key thing is to make sure you setup the clock divider correctly. SPI generally tops out at 16MHz, and is even slower if you have multiple devices on a single master. If you have a substantially faster system clock, you may have pay attention to that.

Reply to
radarman

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