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Xilinx Spartan II pull-up, simple questions

Looking at the mode selection M2 on the SII devices in Xilinx document DS-001_2, table 8, I wonder if the M2 for master mode is correct? It seems to match the rest of the data sheet, but I would have thought the the pullups would always follow the M2 pin and this is the only mode where it does not.

On the SII, there is no mention of allowing for a weak pullup on the global clock lines. Interesting enough that using the 6.x tools and placing the following in the constraints:

NET "p_pclock" LOC = "P88" | IOSTANDARD = LVTTL | PULLUP ;

I get the following message from project manager during place and route:

Annotating constraints to design from file "main.ucf" ... Attached a PULLUP primitive to pad net p_pclock

If I look at the FPGA editor at pin 88 after place and route, there is no dialog box to allow for pullups, etc, like there are with a standard I/O. So, I would have to guess that in the actual device there was no pullup added. Can someone at Xilinx confirm this?

Thanks

Reply to
lecroy
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The M2 does "change its polarity" for pullup control in Master Serial mode. The Mode pin settings were selected to maintain consistency with earlier families, where for example "000" would select Master Serial and "111" would select Slave Serial. The Mode pins should be considered as a group, and not as individual functions, to avoid confusion.

The Spartan-II data sheet does menti> Looking at the mode selection M2 on the SII devices in Xilinx document

-- Marc Baker Xilinx Applications (408) 879-5375

Reply to
Marc Baker

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