Xilinx Spartan II and 5V PCI

PCI spec waveforms (+11V for overshoot, -5.5 for undershoot) are specified at the resistor (55 Ohm for overshoot,

25 Ohm for undershoot) that is part of the test setup, not at the input pin. (section 4.2.1.3)

When you overshoot or undershoot, the clamp diodes pass current causing a voltage drop across the resistor resulting in a reduced voltage seen at the input pin.

-- Paul Fulghum snipped-for-privacy@microgate.com

Said section states that the resistors are voltage source impedances that define the maximum current (ie, the quasi short circuit current that clamping diodes would encounter). That is understood.

Problem here is that the voltage drop depends on the input impedance of the following buffer or hi-z value of a tri-stated output. Given a high impedance input buffer (which is usually the case with CMOS devices) the voltage drop would not occur across the resistor as the relatively low output impedance of the voltage source but the input impedance of the buffer unless there is clamping applied.

The point I was trying to make was that the data sheet does not explicitly tell whether there are clamping diodes in the

5V PCI qualified buffers or not. Since Vcco is 3.3V maximum at the input banks at the FPGA where would the clamping diodes go without a 5V supply given that clamping to 3.3V is impossible ?

Thanks & regards, Christian Boehme

All,

You might try reading the app notes?

Aust> Paul Fulghum wrote:

Again,

Spartan II is identical with Virtex, which means that the clamp diodes can be programmed. Thus the device can operate just fine in the 5V environment, and does meet the overshoot requirement of the PCI test without any concerns.

The app notes deal with components that can not program the clamps,

Aust> All,

The Spartan II datasheet, page 2 of module 2:

Two forms of over-voltage protection are provided, one that permits 5V compliance, and one that does not. For 5V compliance, a zener-like structure connected to ground turns on when the output rises to approximately 6.5V. When 5V compliance is not required, a conventional clamp diode may be connected to the output supply voltage, VCCO.

Page 31 of module 2:

I/Os configured for the PCI, 33 MHz, 5V standard are also

5V-tolerant.

-- Paul Fulghum snipped-for-privacy@microgate.com

That one I did read and considered it for a while but dropped later due to lack of availability of the part.

This one I read also. Too bad that it's not applicable to my problem (namely _5V_ PCI tolerance ;).

-Chris

Clamping diodes only work in 3.3V PCI signaling environments. Since these programmable diodes clamp to Vcco and Vcco is 3.3V it's not too hard to imagine what a 5V steady level would do to the power department ;)

-Chris

Probably slipped through because it says nothing about PCI, hmm ...

^^^^^^^^^^^

Exactly that was the reason for the concern. I have been dealing with ``5V-tolerant'' standard logic (LVCMOS etcpp.) lately where the meaning of that term is technically something completely different from what I would expect from a ``5V-PCI-compliant'' device built in 3.3V technology.

However, apart from the fuzzy 5V compliance and tolerance verbiage in the data sheet, that seems to answer my initial question.

Thanks & regards, Christian Boehme

Hi,

Just to re-state how Virtex and Spartan-II behave, so everyone's on the same page:

When you use the SelectIO Modes "PCI33_3" or "PCI66_3" the clamp diodes are connected to VCCO (3.3v). The device is guaranteed to work in this environment. You would not want to use this in a 5.0v slot.

When you use the SelectIO Mode "PCI33_5" the clamp diodes are not connected. You can use this in a

5.0v slot. The device is guaranteed by Xilinx to work in this environment.

If you are building a universal card, the "right" way to do it is have two designs/bitstreams only differing in what SelectIO Mode is used. Then, at power-on, use an analog comparator to compare the slot's VIO with ~4.15v (make it with a voltage divider...) and load one of two bitstreams based on the result.

Eric

"Christian E. Boehme" wrote:

Christian,

Yes. After I sent the first email, I realized that you were using Spartan II, not 3. Sigh. Next time I will be more careful on the send button. Engage brain.

Virtex and Spartan II are what I call "Classic" FPGA parts: they do 5V PCI, they have hot insertion tri-state behavior, etc. In a way, the last of the great simple FPGAs. Everything since is based on the process technology getting more complicated (not to mention more internal features). In order to stay with high yields, we had to drop the floating outputs (not supported by foundries, so if anything goes wrong, like ESD -- you are on your on, and you own the wafers! which leads to higher costs to customers) as well as other nice features (like

0.35u IO transistors which are bulletproof). But a V1000 is old news, with a million "gates" becoming a small part today. The 2VP7 is now considered a very small part, with 3S1000 being the median member of the Soartan 3 family.

S3 by the way has (finally) passed through the difficult times (first was process a year ago, next was demand was >>> supply). All parts (except one, again due to unprecedented demand) are in stock, and the last two largest family members should be out shortly (3S5000 is just shy of a Virtex 2V6000, or a Virtex II Pro 2VP50 in "gates").

Consult your disti,

Aust> Aust>

Christian,

Yes, power would be the least of your worries: you would be sinking huge currents from the 5V rail to the 3.3V rail. Probably break something.

Aust> Aust>

All,

The zener structure is the ESD protection. It is not a simple zener. It is a complex SCR-zener ESD structure that was designed to pass the PCI requirement, yet also protect the device from ESD. Verrrry tricky. But it works, and gets tested, or it doesn't ship for Spartan II and Virtex.

Eric is right: we stand behind the 5V and 3.3V PCI compliance on S2 and Virtex.

Aust> Paul Fulghum wrote:

The datasheet calls the zener 'overvoltage protection'. Does it work as both overvoltage and ESD protection?

The IBIS file for Spartan-II in the power clamp section of the PCI33_5 model shows that little current (~2 nA) is passed when the pin voltage goes over 6.5V

The ground clamp section shows significant current when pin voltage drops below -0.5V as expected for the ground clamp diode.

How does the zener structure protect from overvoltage if it does not pass significant current?

Is the IBIS file not accounting for the zener structure? Am I misinterpreting the IBIS file?

Thanks, Paul

-- Paul Fulghum snipped-for-privacy@microgate.com

I definately agree the description is fuzzy ;-) Lots of good info in the datasheet, but it sort of dances around that particular issue.

-- Paul Fulghum snipped-for-privacy@microgate.com

Interestingly, that's very simlar to what I actually do right now: I am using two biased comparators comparing PCI 5V with PCI VIO such that even with maximum allowable voltage tolerances the result would be predictably correct. Until now I'd written the first word in config ROM with some well-known header telling the kind of config written to the ROM and warned the user (some LED or whatever) if there was some mismatch with the actual environment. But since there's ample space in the config ROM for at least two complete streams your suggestion is the _definitive_ way to go. It seems that I wasn't dreaming up too unusual things here ;-)

Thanks & regards, Christian Boehme

Spartan II is just perfect for my projects. The one limitation that gave me some headaches and that was the number of different Vcco for IO banks available in PQFP versions (namely 1 ;). But that was about it already. I am actually more constrained by the software tools than by the target hardware.

-Chris