Hi
Sorry to bother the group with something I really should have been able to figure out myself, but I'm sort of pressed for time, so I hope you bear with me.
I have some (limited) knowledge of the (modern) Xilinx Virtex 'Slice', and how it is constructed, so to speak. But how similar is the Altera FPGAs' building blocks, and what are they called?
Oh, and how, if at all, similar are the two?
I find it a bit difficult to learn all the ins and outs of each companies differnt products, so I don't blame you for asking here. But check with the data sheets to really understand it all.
The Xilinx slice is composed of a pair of LUTs, a pair of FFs, carry chain and some other misc logic to optimize 5 input functions and other similar operations. There are different numbers of slices to a CLB depending on the family, 1, 2 or 4 slices.
Altera calls a LUT plus FF an LE. LEs are grouped into Logic Array Blocks (LABs) of 8 or 10 LEs depending on the family. There are two chains within a LAB, a fast carry like the Xilinx also a "Cascade" chain for doing large functions. This is similar to the way Xilinx can combine LUTs within a CLB, but runs the length of the LAB and implements a very fast, two input AND gate at each LUT output.
You can analyze the differences on paper all day, and you still won't know how your design will do in either family of parts. The best thing to do is to write your HDL to be generic and see how it fits.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
"rickman" wrote [......]
Thanks a lot!
Sure, and normally I would. But I've studied a paper written by François-Xavier Standaert, where he and some other reasearchers optimizes a implementation of the Rijndael algorithm to better match the Xilinx slice. And the results are impressive!
So I wanted to try and figure out how I could transfer such a design strategy to the Altera-FPGA I am working on (EPXA1F484C1). But in order to do that, I need to understand how I can make the different stages fit in Alteras slice-equivalent :p
I will try and grab a detailed data sheet from Alteras website, allthough I have downloaded all the documentation marked for EPXA1, and haven't seen anything like it in there. But I suppose that if I search for LC or LAB layout or something similar, I will eventually find it :-)
-"Panic"
I understand. The data sheet is just a start in learning about optimizing a design. The routing is also important which is not described. What aspect are you trying to optimize? Speed, size? What Xilinx CLB features did they optimize for? There are only a few significant differences in the two brands, but they can be *very* significant depending on the design. Just ask Ray Andraka.
BTW, do you have the part number scrambed? Alteras part numbers are mostly EPxy where x is a number and letter and denotes the product line line while y is a number indicating the size. Example, EP2A40 is an APEX II at 3 million gates.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Opps, nevermind to this last part. I searched on the Altera site and found that this is an Excalabur part with built in ARM CPU. I did not have this one on my hard drive. The architecture of the LABs is the same as the APEX 20KE. Download that data sheet and you should find what you are looking for.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
"rickman" wrote
I'll do that. Thanks a lot :-)
Well said.
Working generic synth code cuts through technobabble like a knife. It tests the tools and the device from front to back and provides utilization and fmax benchmarks that you just can't get any other way.
That said, I have noticed that Altera's ep1s series is much more Xilinx-like than ep20k.
-- Mike Treseler
Rick,
Altera's part numbering changed after Apex to give a rough estimate of LE count (LE count * 1000 actually), rather than an ASIC-like gate count (i.e., 20K200E = Apex 20KE family, ~200K gates). That 20K200E apex chip had ~8k LEs... a similar-sized (well, a little larger) device in terms of LE count is the Stratix 1S10 -- 1S meaning the family, (Stratix 1st edition), and 10 meaning ~10K LEs in the device. So, a 1S40 has about 40,000 LEs, and a Cyclone 1C6 has about 6,000 LEs, and so forth.
The device Mr(s). Panic refers to is the Excalibur XA1, where XA is the family name "for Excalibur Arm". The family has EPXA1, XA4, and XA10 devices, where the number is related to gate count (gate count /
100K). The XA1 is sort of like the 20K100E, but with the ARM CPU aboard. The Excalibur family is based on the Apex 20KE FPGA fabric, and thus the gate count terminology was still used.Anyways, even though I work here I am very happy we number the parts now with respect to the number of logic elements inside. Nice and simple.
Jesse Kempa Altera Corp. jkempa at altera dot com
As long as I have the attention of someone from Altera, let me make an observation about the Excalibur parts.
This is a part that I could use on my current board since I have an ARM MCU along with an FPGA in direct connection using the same power supplies. Having only a single package would save me board space (in theory) and being on a single chip should save me power and cost (again in theory). I am currently looking at power consumption of about 100 to
300 mW (won't know for sure until it is built) and the combination will cost me about $30.Your smallest Excalibur, as you say, is the EPXA1. It comes in a 484 pin package (23 x 23 mm), costs over $100 and will use Watts, not mWatts. Unfortunatly this is way too much chip in every respect and since it is not 5 volt tolerant, I would have to add buffering taking up any board space I might save.
Is there any plans for a lower end combination of 50 MHz ARM 7 perhaps with FPGA in a reasonably sized package with a lower power curve? Even if 5 volt tolerance is not an option, such a part with a reasonable price tag could save lots of space on a board. To be honest, I just can't see paying triple the price for a combined part especially when it still requires an external Flash which is included with an ARM MCU.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
"Jesse Kempa" wrote
Hehe. I might be a bit on the feminine side, but I'm not a full blown woman. Yet anyway :-P
Hmmm. You wouldn't happen to know of some documents that would answer my question (OP)? Working "over there" and all...?
-Panic
--
--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
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