Xilinx S3 I/O robustness question - Page 4

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Re: Xilinx S3 I/O robustness question

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I also haven't heard of this before.  But then, I haven't used 90nm
parts before.
Perhaps this is the way of the future.


Re: Xilinx S3 I/O robustness question
Hi Rick,
     Here are things that I agree completely with you on. "No amount
of simulation will correct a problem if you don't understand what is
going on." and "I can do a few simple calculations to get worst case
numbers for ringing on a 6" trace.". Without first understanding
what's going on, the simulator can be a dangerous thing. Garbage in,
garbage out! I think it's absolutely vital to know what's going on or
how will you be able to sanity check the results the simulator gives?
      cheers, Syms.

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Re: Xilinx S3 I/O robustness question
That was some good reading!  Thanks to everyone who had input on this

I would like to know more details about how the S3 I/O models are
being maintained.  I can't seem to get Xilinx to keep up with their
timing models in their own tools.

If the S3 really is that sensitive, I would not use simulation as the
last word.  While we have more "sensitive" boards tested at the
supplier's, even this may no longer be "good enough" to validate the
PCB. And if they hit 10% on their test pads I think they are doing

My big fear is that while we have been doing 1G digital designs for
several years using ECL without any problems (well), as we migrate to
putting these designs into faster FPGAs that we may loose reliablity.
The best thing we could hope for is for the FPGA designers to make a
quantum jump to 100GHz+ internal routing and take all the fun out of
the layout. And while your at it, there are some other features I
would like packed in there as well.  Maybe I will live to be that old,
but I don't think so.

Thanks again for putting some light on this.

Re: Xilinx S3 I/O robustness question
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I did not say that "ringing is the cause of crosstalk."  I said that
another SI issue that you ought to be concerned about is crosstalk.  I
then went on to say that, because of crosstalk, we saw that the
badness on the data lines was being coupled to a reset line.

And, yes, simulation showed us exactly what was going on.

I'm sorry if I wasn't clear.

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Like I said -- consider that Xilinx are erring on the side of caution.
 And, as Austin points out, one can minimize the possibility of this
sort of potential damage by performing the appropriate SI simulations,
and adjusting the layout as needed.
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Again, his comments are that as chip geometries shrink and rise times
get faster, one needs to consider SI issues everywhere.   Erring on
the side of caution.

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You know your needs better than the rest of us; I can't argue with

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Ah, but you can, if you can obtain a model of the connector you're
going to use, and assume that you've got a perfect load on the other
side.  Better than nothing.  You can also deviate from "perfection"
and see the effects on your board.


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