Xilinx S3 I/O robustness question

When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the output voltage, VCCO, must be within the "narrow" voltage range defined in the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal

3.3V value.

The primary consideration on Spartan-3 I/Os is to keep the voltage at the pin below the 3.75V absolute maximum specification. Going above 3.75V doesn't immediately destroy the device, but prolonged exposure degrades device lifetime. If the voltage remains below 3.75V, there is no degradation.

So, if VCCO should be below 3.45V, how can the voltage at the pin possible reach 3.75V? Mismatched impedance can cause overshoot and undershoot, raising the voltage on the pin by hundreds of millivolts. Properly terminating a trace eliminates or reduces the over/undershoot to acceptable limits. Application note XAPP659 describes some of the techniques to guarantee that signals stay under 3.75V. Although written for the Virtex-II Pro family, these same techniques apply to Spartan-3 FPGAs.

Using 3.3V I/O Guidelines in a Virtex-II Pro Design.

I hadn't seen this question coming in from our FAE team, so my apologies on not receiving an answer before this time. Should you have any other questions, please feel free to contact me directly. Just be sure to remove the "NOSPAM" from my return E-mail address.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

Steve, keep in mind I am talking about the reflected signal on an output only. I was provided the following link from Xilinx. Does this refer to the S3 devices as well, as it conflicts with your original responce?

Problem Description:

Keywords: FPGA, overshoot, undershoot, reliability

Urgency: Standard

General Description: Does ringing (overshoot and undershoot) compromise the reliability of an FPGA device?

Solution 1:

For all FPGA families, ringing signals are not a cause for reliability concerns. To cause such a problem, the Absolution Maximum DC conditions need to be violated for a considerable amount of time (seconds).

Keep in mind, however, that ringing can create many functional issues, causing glitches, double- clocking, setup/hold errors, etc.

A19BB13C19BA9C4BB84FDCD0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit

All,

A reflection back to an output should not cause a problem, as the nmos is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd or Vcco. If, however, the reflections have enough current to pump up the Vcco, then you have to be careful you do not exceed the max Vcco voltage.

It is not recommended to have poor signal integrity (ie unterminated fast edge rate signals) in any design, let alone S3.

Aust> > When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the

Austin,

I am guessing that you did not work on the design for the S3. Xilinx has told me everything from there would be no adverse effect from a mismatched output, to causing complete failure. I have kept all of the correspondences if you would like me to post them, but I really don’t see the value in doing so. I am not sure why they seem unable to come up with an answer that they all agree upon.

I do not agree with your statement “…, as the nmos is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd or Vcco.” . If we look at an example of an I/O pin (so not a dedicated output), when we transition from a low to high state on the output, the high side driver is sourcing current to the load. As the signal propagates down our transmission line and reaches the end, some energy will reflect back. Let’s use a very high impedance for our termination, so the reflected signal is in phase with the incident. As the reflected signal reaches the output pin it will raise the voltage. Because the driver is sourcing, it has no way to clamp this transient. So, the catch diodes would clamp the reflected signal to a level just over the supply voltage.

It’s nice to make the comment about “is not recommended to have poor signal integrity”, but it does not help with the problem. If the devices MTBF decreases with the amount of reflected energy, it would be good to know how close the impedance must be matched. Let’s say you did all of your homework in the layout. You have simulated every trace. Even so, most of the board houses will not guarantee a perfect board is made. There will be a tolerance for the board. Especially if you are playing around with FR-4. So, then we have to ask how close do we need to match the impeadances before we start to see an increase in the failure rates.

If this is really an issue with the S3, it will be the first time I have seen this in a digital device. I have seen damage to some higher-powered RF output devices when they have not been matched correctly, due to overheating. Maybe the S3 is so sensitive that it can be damaged this way. Had they not mentioned the S3 being so sensitive during their presentation, I would not have tried to investigate it.

Well, Xilinx, can you come up with an answer that you KNOW is correct?

This is a fairly common misconception. A p-channel output transistor, when active, has a certain impedance, say

10 Ohm. It sources and also sinks current with that impedance . All MOS transistors behave like resistors (at least over a certain voltage range). They conduct current in BOTH directions. Therefore, the active p-channel output transistor will snub the incoming reflection. If you don't believe it, just try it out. It's a simple enough experiment.

Peter Alfke, Xilinx Applications

I just got the following e-mail..... It has some data, but a better article may have been:

I am still looking for an answer to my question.

This is a l>

This is a fairly common misconception. A p-channel output transistor, when active, has a certain impedance, say

10 Ohm. It sources and also sinks current with that impedance . All MOS transistors behave like resistors (at least over a certain voltage range). They conduct current in BOTH directions. Therefore, the active p-channel output transistor will snub the incoming reflection. If you don't believe it, just try it out. It's a simple enough experiment.

Peter Alfke, Xilinx Applications

Let me help you, and rephrase your original question: If a 3.3 V output on Spartan3, going active Low to active High, drives a transmission line of arbitrary length that is open ended at the far end, there will be a return signal that wants to pull the 3S pin higher than Vcco = 3.3 V. Can this cause do damage to the Spartan3 pin?

My answer would be: NO. The return> I am still looking for an answer to my question.

There is nothing special about Spartan or FPGAs in this area. Right?

Is there a general rule in output pad design that the pad must be rugged enough so that it can't shoot itself in the foot with its own reflections? (I don't remember seeing any warnings about this in data sheets.)

What about busses, like PCI, where the driver might be in the middle so the effective line impedance is half of the nominal 50 ohms. (Can it get even lower than that due to capicative loading?)

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What happens at 25 ohms??

This is what I have been running into. There seems to be no one at Xilinx who is sure. I had hoped that with this news group being a bit more visable that I could find the right person to ask. Here is David Anderson’s and Paul’s (who both work for Xilinx) responses which are different from yours. In Paul's note, he even talks about asking the factory.

*****************************************

So yes the reflected energy can still cause damage, but again if you limit the current to 10mA there shouldn't be any damage. This will be the same limitations as if this was an input. So you can refer to the max specs in the first page of the datasheet. See link below:

Mainly you need to take a look at Vin and note 4. When VCCO is 3.0 V or less, VIN overshoot may go as high as VCCO + 1.0 V for up to 11 ns provided that the current entering the I/O pin is limited to 10 mA. Also, when VCCO is 3.0 V or less, VIN undershoot may go as low as -1.0 V for up to 11 ns provided that the current entering the I/O pin is limited to 10 mA.

Hope this helps.

Regards, David Anderson

*****************************************

Going back to your original question, the answer back from the factory is at

3.3 V signaling, it is possible to have reflections damage the part. If you have a particular circuit that you would like to model for you we can do that.

In general, IBIS simulation is the way to go in, to insure signal integrity (especially for high speed designs). It should be possible to use the XCITE technology to use a few resistors to impedance match the board layout, assuming that most trace lengths are about the same. Should a few signals be much longer/shorter, XCITE or DCI can be disabled on an IO by IO basis, and these pins can then be terminated separately, if necessary (do IBIS simulation to see if overshoot will be a problem).

Hope this helps, Paul

*****************************************

I know we have gone back and forth on this, but I think the answer is that there is not an issue. The from what I have seen, the IO on the Spartan III are speced the same as the Virtex II Pro, regarding maximum voltage, and reflections are not an issue with Virtex II Pro.

Brain,

Please correct me if I am wrong. Again, I believe the initial response was wrong, and that reflections cannot damage the IO. Also, what data can we provide that backs our position.

Thanks, Paul

Well, let's see if they can answer this. My fear was that they boasted about their lastest 90nm technology and then turned around and made a comment about how sensitive it is to transients.

I agree, a very interesting question.

PCI requires that the input withstands higher voltages during 11ns, if I recall correctly.

Homann

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d0asta@dtek.chalmers.se

Hello,

There seems to be a great deal of interest on this topic.

I can tell you what I believe to be the case, and I invite others from Xilinx to correct what I write here, if I make any errors. Most of this I have learned from others. As I do not specify or guarantee device behavior, the device datasheet takes precedence over anything I might say...

In devices like V2Pro and S3, the maximum allowed voltages (both positive and negative) on the I/O pins form a smaller window than in some previous families. In the I/O itself, there are structures that experience a "stress" that is:

• Pin voltage above GND.

• Pin voltage below VCCO.

When you are using a VCCO of 3.3 volts, you must be diligent in your board design so that you do not have big reflections from signal integrity problems. If you have severe reflections when using a VCCO of 3.3 volts, you can possibly exceed the maximum ratings of the device. Yes, there are diode clamps on the pin, to both VCCO and GND, but with a VCCO of 3.3v, the clamps will allow the voltage to rise above the maximum rating of the device when VCCO is 3.3 volts.

So, when using a VCCO of 3.3v, it is a wise idea to simulate the I/O you are using, along with your board, to make sure you are operating the device within the maximum ratings. I think this homework is worthwhile, even in other cases.

If IBIS models aren't your thing, and you can't be bothered with them, you can read XAPP659 for pre-engineered solutions.

This is discussed in detail in XAPP653. You use a VCCO of

3.0 volts. It works, is PCI compliant (even if the PCI bus voltage VIO, which is an independent supply, rises as high as 3.6 volts -- which is allowed). Xilinx has verified this in hardware. The concept is that lowering VCCO to 3.0v reduces the "stress" applied:

• (Pin voltage above GND) by clamp diode to VCCO = 3.0v.

• (Pin voltage below VCCO) by reduced VCCO = 3.0v.

An added benefit of our I/O design is that all programmable I/O are identical, so you won't find yourself forced into a larger part if (for example) you need more PCI capable I/O.

It is unfortunate that someone (incorrectly) suggested the device I/O is not "robust". It is robust, and guaranteed by Xilinx, when you use it as directed in the FPGA device datasheet.

Hope that helps, Eric

Is that window just smaller in terms of volts, or is it smaller in terms of percent?

Why wasn't this a problem several years ago? Consider a 5V IOB or junk CMOS logic. It would get pulsed to 10 V from nasty reflections if the clamp diodes didn't do their thing. Clearly that's way above the max ratings. So we have been operating out-of-spec for a long time.

Has technology in this area changed in the past few years? Have I missed similar discussions in other areas? (That would be easy.)

Is there something about the way transistors scale that I don't know about? (yet) Are fab lines cutting things closer now? ...

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Hello Xilinx, are you there???

lecroy,

Of course we are here, and reading.

The confusion is (to many) that the question is what does the reflection back to the driver do to the driver, right? This is a fairly obscure distinction, so I would not expect every one of the 200+ hotline CAEs to get it perfectly right on the first try.

Did you submit multiple cases? Or call some folks you know? (IE how did you get multiple answers...) It would help if you worked this thru the hotline, as they need to learn from their mistakes, and improve their service sometimes. If you are talking about it here, then we are not closing the loop!

Well, if the PMOS is ON, then it is really hard for a reflection to drive the output pin to a voltage that is higher than the specification. Conversely, if the NMOS is ON, then it is really hard for the reflection to drive the output pin below ground.

Look at the IBIS simulation at the output pin to see what the voltage excursions are, an be sure they stay within the specifications sheet and user's guide.

If you have a specific waveform, you may email it to me directly, and I will get the "final word" from the designers and technology groups.

But let me know the case number, so I can make sure that the hotline is kept in the loop.

Aust> Hello Xilinx, are you there???

Hi Peter, If the pin has 10 Ohms of drive impedance the initial sent pulse will be less than 3.3V, in fact 3.3V * 50/(10+50) = 2.75V, as the 10 Ohms driver drives a 50 Ohm line. The reflected signal from the unterminated far end is then 2* 2.75V = 5.5V. This reflected pulse then increases the voltage at the pin to 3.667, as it's driven from 50 Ohms into a 10 Ohm impedance to VCC = 3.3V. This is less than the absolute maximum rating of 3.75V. Hooray! As you say, this calculation disregards the attenuation due to the trace propagation function, which will further reduce the amplitude of the pulse as it travels back and forth down the transmission line(pcb trace). This is caused by skin effect and stuff. I guess you could also reduce the drive strength of the pin from the default 12mA, to increase the source impedance. The receiver pin is the one that gets the big hit. cheers, Symon.

Symon,

As if often the case, if you do not run a simulation, you will not get results that are even close to the truth (by guessing at what is happening).

With a driver impedance of 8.8 ohms (from IBIS simulation), the overshoot/undershoot back at the driver is less than 100 mV (no pcb or t-line losses, IBIS done with Hyperlynx).

Why does this not scale exactly as you state? Because the ON resistance of the transistors is not very linear, and they are less than 8.8 ohms near Vcc or ground.

So, unless you simulate the actual circuit, you will not get the actual result.

Aust> Hi Peter,

So how bad is that hit? How good are the protection diodes?

If the clamp diodes are any good they will reduce the reflection and make things easier back at the transmitter.

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Hal,

Simulation includes a receiver at the end of a 2ns line, and you are correct, it makes things better.

Why simulate a driver drving nothing? Unless of course that is a possibility in a system....not a very useful system, though....

Aust> > The receiver pin is the one that gets the big hit.