Xilinx S3 I/O robustness question

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I have spent the last 60 days trying to get an answer from Xilinx on
their new S3 devices.  During a review, it was stated that the new S3s
were very sensitive to transients on the I/O pins. Because they made a
point to mention this during the review, I posed the following
question to Xilinx:

"If we look at the incident versus reflected energy and tune the stub
(trace)
for a worst case match is it possible the driver could be damaged or
the
chip lock up due to the reflected energy?"

"The circuit would be as follows:
Spartan III    Output  ------------------------------ Tunable Stub"

I wonder if anyone in this group has asked this question and what was
the responce from Xilinx?

Re: Xilinx S3 I/O robustness question
When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the
output voltage, VCCO, must be within the "narrow" voltage range defined in
the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal
3.3V value.

The primary consideration on Spartan-3 I/Os is to keep the voltage at the
pin below the 3.75V absolute maximum specification.  Going above 3.75V
doesn't immediately destroy the device, but prolonged exposure degrades
device lifetime.  If the voltage remains below 3.75V, there is no
degradation.

So, if VCCO should be below 3.45V, how can the voltage at the pin possible
reach 3.75V?  Mismatched impedance can cause overshoot and undershoot,
raising the voltage on the pin by hundreds of millivolts.  Properly
terminating a trace eliminates or reduces the over/undershoot to acceptable
limits.  Application note XAPP659 describes some of the techniques to
guarantee that signals stay under 3.75V.  Although written for the Virtex-II
Pro family, these same techniques apply to Spartan-3 FPGAs.

Using 3.3V I/O Guidelines in a Virtex-II Pro Design.
http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf

I hadn't seen this question coming in from our FAE team, so my apologies on
not receiving an answer before this time.  Should you have any other
questions, please feel free to contact me directly.  Just be sure to remove
the "NOSPAM" from my return E-mail address.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC



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Re: Xilinx S3 I/O robustness question
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Steve, keep in mind I am talking about the reflected signal on an
output only.  I was provided the following link from Xilinx.  Does
this refer to the S3 devices as well, as it conflicts with your
original responce?



http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath11%001

     Problem Description:

Keywords: FPGA, overshoot, undershoot, reliability

Urgency: Standard

General Description:
Does ringing (overshoot and undershoot) compromise the reliability of
an FPGA device?

Solution 1:

For all FPGA families, ringing signals are not a cause for reliability
concerns. To cause such
a problem, the Absolution Maximum DC conditions need to be violated
for a considerable
amount of time (seconds).

Keep in mind, however, that ringing can create many functional issues,
causing glitches, double-
clocking, setup/hold errors, etc.

Re: Xilinx S3 I/O robustness question

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Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

All,

A reflection back to an output should not cause a problem, as the nmos is ON, or
the pmos is ON, effectively
clamping the IOB pin to either gnd or Vcco.  If, however, the reflections have
enough current to pump up the
Vcco, then you have to be careful you do not exceed the max Vcco voltage.

It is not recommended to have poor signal integrity (ie unterminated fast edge
rate signals) in any design, let
alone S3.

Austin

lecroy wrote:

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http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath11%001
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Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
All,
<p>A reflection back to an output should not cause a problem, as the nmos
is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd
or Vcco.&nbsp; If, however, the reflections have enough current to pump
up the Vcco, then you have to be careful you do not exceed the max Vcco
voltage.
<p>It is not recommended to have poor signal integrity (ie unterminated
fast edge rate signals) in any design, let alone S3.
<p>Austin
<p>lecroy wrote:
<br>> When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application,
the
<br>> output voltage, VCCO, must be within the "narrow" voltage range defined
in
<br>> the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with
a nominal
<br>> 3.3V value.
<br>>
<br>> The primary consideration on Spartan-3 I/Os is to keep the voltage
at the
<br>> pin below the 3.75V absolute maximum specification.&nbsp; Going above
3.75V
<br>> doesn't immediately destroy the device, but prolonged exposure degrades
<br>> device lifetime.&nbsp; If the voltage remains below 3.75V, there
is no
<br>> degradation.
<br>>
<br>> So, if VCCO should be below 3.45V, how can the voltage at the pin
possible
<br>> reach 3.75V?&nbsp; Mismatched impedance can cause overshoot and undershoot,
<br>> raising the voltage on the pin by hundreds of millivolts.&nbsp; Properly
<br>> terminating a trace eliminates or reduces the over/undershoot to
acceptable
<br>> limits.&nbsp; Application note XAPP659 describes some of the techniques
to
<br>> guarantee that signals stay under 3.75V.&nbsp; Although written for
the Virtex-II
<br>> Pro family, these same techniques apply to Spartan-3 FPGAs.
<br>>
<br>> Using 3.3V I/O Guidelines in a Virtex-II Pro Design.
<br>> <a
href="http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf ">http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf </a>

<br>>
<p>Steve, keep in mind I am talking about the reflected signal on an
<br>output only.&nbsp; I was provided the following link from Xilinx.&nbsp;
Does
<br>this refer to the S3 devices as well, as it conflicts with your
<br>original responce?
<p><a
href="http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath11%001 ">http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&amp ;iCountryID=1&amp;getPagePath11%001</a>
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Problem Description:
<p>Keywords: FPGA, overshoot, undershoot, reliability
<p>Urgency: Standard
<p>General Description:
<br>Does ringing (overshoot and undershoot) compromise the reliability
of
<br>an FPGA device?
<p>Solution 1:
<p>For all FPGA families, ringing signals are not a cause for reliability
<br>concerns. To cause such
<br>a problem, the Absolution Maximum DC conditions need to be violated
<br>for a considerable
<br>amount of time (seconds).
<p>Keep in mind, however, that ringing can create many functional issues,
<br>causing glitches, double-
<br>clocking, setup/hold errors, etc.</blockquote>
</html>

--------------A19BB13C19BA9C4BB84FDCD0--


Re: Xilinx S3 I/O robustness question
Austin,

I am guessing that you did not work on the design for the S3.  Xilinx
has told me everything from there would be no adverse effect from a
mismatched output, to causing complete failure.  I have kept all of
the correspondences if you would like me to post them, but I really
don&#8217;t see the value in doing so.  I am not sure why they seem
unable to come up with an answer that they all agree upon.

I do not agree with your statement &#8220;&#8230;, as the nmos is ON,
or the pmos is ON, effectively clamping the IOB pin to either gnd or
Vcco.&#8221; .   If we look at an example of an I/O pin (so not a
dedicated output), when we transition from a low to high state on the
output, the high side driver is sourcing current to the load.  As the
signal propagates down our transmission line and reaches the end, some
energy will reflect back.  Let&#8217;s use a very high impedance for
our termination, so the reflected signal is in phase with the
incident.  As the reflected signal reaches the output pin it will
raise the voltage.  Because the driver is sourcing, it has no way to
clamp this transient.  So, the catch diodes would clamp the reflected
signal to a level just over the supply voltage.

It&#8217;s nice to make the comment about  &#8220;is not recommended
to have poor signal integrity&#8221;, but it does not help with the
problem.  If the devices MTBF decreases with the amount of reflected
energy, it would be good to know how close the impedance must be
matched.  Let&#8217;s say you did all of your homework in the layout.
You have simulated every trace.  Even so, most of the board houses
will not guarantee a perfect board is made. There will be a tolerance
for the board.  Especially if you are playing around with FR-4.  So,
then we have to ask how close do we need to match the impeadances
before we start to see an increase in the failure rates.

If this is really an issue with the S3, it will be the first time I
have seen this in a digital device.  I have seen damage to some
higher-powered RF output devices when they have not been matched
correctly, due to overheating.  Maybe the S3 is so sensitive that it
can be damaged this way. Had they not mentioned the S3 being so
sensitive during their presentation, I would not have tried to
investigate it.

Well, Xilinx, can you come up with an answer that you KNOW is correct?

Re: Xilinx S3 I/O robustness question
This is a long and complex e-mail.
Let me just correct one fundamental popular misconception below:

lecroy wrote:
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This is a fairly common misconception.
A p-channel output transistor, when active, has a certain impedance, say
10 Ohm. It sources and also sinks current with that impedance . All MOS
transistors behave like resistors (at least over a certain voltage
range). They conduct current in BOTH directions. Therefore, the active
p-channel output transistor will snub the incoming reflection.
If you don't believe it, just try it out. It's a simple enough experiment.

Peter Alfke, Xilinx Applications

Re: Xilinx S3 I/O robustness question
I just got the following e-mail.....  It has some data, but a better
article may have been:

http://support.xilinx.co.jp/xapp/xapp329.pdf

I am still looking for an answer to my question.





This is a long and complex e-mail.
Let me just correct one fundamental popular misconception below:

lecroy wrote:
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This is a fairly common misconception.
A p-channel output transistor, when active, has a certain impedance,
say
10 Ohm. It sources and also sinks current with that impedance . All
MOS
transistors behave like resistors (at least over a certain voltage
range). They conduct current in BOTH directions. Therefore, the active
p-channel output transistor will snub the incoming reflection.
If you don't believe it, just try it out. It's a simple enough
experiment.

Peter Alfke, Xilinx Applications

Re: Xilinx S3 I/O robustness question
Let me help you, and rephrase your original question:
If a 3.3 V output on Spartan3, going active Low to active High, drives a
transmission line of arbitrary length that is open ended at the far end,
there will be a return signal that wants to pull the 3S pin higher than
Vcco = 3.3 V.
Can this cause do damage to the Spartan3 pin?

My answer would be: NO.
The returning 3.3V wave wants to pull the pin to 6.6 V, but the
transmission line impedanec is roughly 50 Ohm, and the chip pull-up
impedance is roughly 10 Ohm, so you have a voltage divider that raises
the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The
resulting theoretical 3.85 voltage is really a bit lower since the
reflection is not perfect, and there are losses on the line.
Also, this spike will only last a few nanoseconds.
I would say that this poses no problem. But I have copied Steve Knapp,
who handles Spartan applications. He may add his opinion to this.

Peter Alfke, Xilinx
=============================
lecroy wrote:
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Re: Xilinx S3 I/O robustness question
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There is nothing special about Spartan or FPGAs in this area.  Right?

Is there a general rule in output pad design that the pad must
be rugged enough so that it can't shoot itself in the foot with
its own reflections?  (I don't remember seeing any warnings about
this in data sheets.)

What about busses, like PCI, where the driver might be in the middle
so the effective line impedance is half of the nominal 50 ohms.
(Can it get even lower than that due to capicative loading?)

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Re: Xilinx S3 I/O robustness question
snipped-for-privacy@suespammers.org (Hal Murray) wrote in message
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Well, let's see if they can answer this. My fear was that they boasted
about their lastest 90nm technology and then turned around and made a
comment about how sensitive it is to transients.
 
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I agree, a very interesting question.

Re: Xilinx S3 I/O robustness question
snipped-for-privacy@chek.com (lecroy) writes:

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PCI requires that the input withstands higher voltages during 11ns, if
I recall correctly.

Homann
--
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snipped-for-privacy@dtek.chalmers.se

Re: Xilinx S3 I/O robustness question

Hello,

There seems to be a great deal of interest on this topic.

I can tell you what I believe to be the case, and I invite
others from Xilinx to correct what I write here, if I make
any errors.  Most of this I have learned from others.  As
I do not specify or guarantee device behavior, the device
datasheet takes precedence over anything I might say...

In devices like V2Pro and S3, the maximum allowed voltages
(both positive and negative) on the I/O pins form a smaller
window than in some previous families.  In the I/O itself,
there are structures that experience a "stress" that is:

* Pin voltage above GND.
* Pin voltage below VCCO.

When you are using a VCCO of 3.3 volts, you must be diligent
in your board design so that you do not have big reflections
from signal integrity problems.  If you have severe reflections
when using a VCCO of 3.3 volts, you can possibly exceed the
maximum ratings of the device.  Yes, there are diode clamps
on the pin, to both VCCO and GND, but with a VCCO of 3.3v,
the clamps will allow the voltage to rise above the maximum
rating of the device when VCCO is 3.3 volts.

So, when using a VCCO of 3.3v, it is a wise idea to simulate
the I/O you are using, along with your board, to make sure
you are operating the device within the maximum ratings.  I
think this homework is worthwhile, even in other cases.

If IBIS models aren't your thing, and you can't be bothered
with them, you can read XAPP659 for pre-engineered solutions.

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This is discussed in detail in XAPP653.  You use a VCCO of
3.0 volts.  It works, is PCI compliant (even if the PCI
bus voltage VIO, which is an independent supply, rises as
high as 3.6 volts -- which is allowed).  Xilinx has verified
this in hardware.  The concept is that lowering VCCO to 3.0v
reduces the "stress" applied:

* (Pin voltage above GND) by clamp diode to VCCO = 3.0v.
* (Pin voltage below VCCO) by reduced VCCO = 3.0v.

An added benefit of our I/O design is that all programmable
I/O are identical, so you won't find yourself forced into a
larger part if (for example) you need more PCI capable I/O.

It is unfortunate that someone (incorrectly) suggested the
device I/O is not "robust".  It is robust, and guaranteed
by Xilinx, when you use it as directed in the FPGA device
datasheet.

Hope that helps,
Eric

Re: Xilinx S3 I/O robustness question
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Is that window just smaller in terms of volts, or is it
smaller in terms of percent?

Why wasn't this a problem several years ago?  Consider
a 5V IOB or junk CMOS logic.  It would get pulsed to 10 V from
nasty reflections if the clamp diodes didn't do their thing.
Clearly that's way above the max ratings.  So we have been
operating out-of-spec for a long time.

Has technology in this area changed in the past few years?
Have I missed similar discussions in other areas?  (That
would be easy.)

Is there something about the way transistors scale that
I don't know about? (yet)  Are fab lines cutting things
closer now?  ...

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other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
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Re: Xilinx S3 I/O robustness question

What happens at 25 ohms??


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This is what I have been running into.  There seems to be no one at
Xilinx who is sure. I had hoped that with this news group being a bit
more visable that I could find the right person to ask.  Here is David
Anderson&#8217;s and Paul&#8217;s (who both work for Xilinx) responses
which are different from yours.  In Paul's note, he even talks about
asking the factory.



*****************************************

So yes the reflected energy can still cause damage, but again if you
limit
the current to 10mA there shouldn't be any damage.  This will be the
same
limitations as if this was an input.  So you can refer to the max
specs
in the first page of the datasheet.  See link below:
http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
Mainly you need to take a look at Vin and note 4. When VCCO is 3.0 V
or
less, VIN overshoot may go as high as VCCO + 1.0 V for up to 11 ns
provided
that the current entering the I/O pin is limited to 10 mA. Also, when
VCCO
is 3.0 V or less, VIN undershoot may go as low as -1.0 V for up to 11
ns
provided that the current entering the I/O pin is limited to 10 mA.

Hope this helps.

Regards,
David Anderson

*****************************************


Going back to your original question, the answer back from the factory
is at
3.3 V signaling, it is possible to have reflections damage the part.
If you have a particular circuit that you would like to model for you
we can
do that.

In general,  IBIS simulation is the way to go in, to insure signal
integrity
(especially for high speed designs).  It should be possible to use the
XCITE
technology to use a few resistors to impedance match the board layout,
assuming that most trace lengths are about the same.  Should a few
signals be
much longer/shorter, XCITE or DCI can be disabled on an IO by IO
basis, and
these pins can then be terminated separately, if necessary (do IBIS
simulation to see if overshoot will be a problem).

Hope this helps,
Paul

*****************************************


I know we have gone back and forth on this, but I think the answer is
that
there is not an issue.  The from what I have seen, the IO on the
Spartan III
are speced the same as the Virtex II Pro, regarding maximum voltage,
and
reflections are not an issue with Virtex II Pro.

Brain,

Please correct me if I am wrong.  Again, I believe the initial
response was
wrong, and that reflections cannot damage the IO.  Also, what data can
we
provide that backs our position.

Thanks,
Paul

Re: Xilinx S3 I/O robustness question
Hello Xilinx, are you there???  



snipped-for-privacy@chek.com (lecroy) wrote in message
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Re: Xilinx S3 I/O robustness question
lecroy,

Of course we are here, and reading.

The confusion is (to many) that the question is what does the reflection back to
the driver do to the
driver, right?  This is a fairly obscure distinction, so I would not expect
every one of the 200+ hotline
CAEs to get it perfectly right on the first try.

Did you submit multiple cases?  Or call some folks you know?  (IE how did you
get multiple answers...) It
would help if you worked this thru the hotline, as they need to learn from their
mistakes, and improve
their service sometimes.  If you are talking about it here, then we are not
closing the loop!

Well, if the PMOS is ON, then it is really hard for a reflection to drive the
output pin to a voltage that
is higher than the specification.  Conversely, if the NMOS is ON, then it is
really hard for the reflection
to drive the output pin below ground.

Look at the IBIS simulation at the output pin to see what the voltage excursions
are, an be sure they stay
within the specifications sheet and user's guide.

If you have a specific waveform, you may email it to me directly, and I will get
the "final word" from the
designers and technology groups.

But let me know the case number, so I can make sure that the hotline is kept in
the loop.

Austin

lecroy wrote:

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Re: Xilinx S3 I/O robustness question
I have been away, but was glad to see people are starting to talk
about this possible issue with the S3.

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to the driver do to the
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every one of the 200+ hotline
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get multiple answers...) It
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their mistakes, and improve
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closing the loop!

Well, like I had stated early on, I had spent about two months working
the channels at Xilinx trying to get an answer, starting with the
person who made the original comment about it being a problem.  I
never opened a case with the hotline.  I have never found them to be
useful and it seems their only goal to it to close as many calls as
possible, not help the customers.  That's for a different topic.

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output pin to a voltage that
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really hard for the reflection
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excursions are, an be sure they stay
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Well, not like Mr. Pease, I have always been a big user of simulation
as one tool.  Certainly, not the last tool and I don't see it
replacing the VNA any time soon as a way to get the 'real' picture of
what is going on.  But the question I always have when some one throws
out the simulation card is how good is your model.  When Xilinx
released the IBIS models for the S3, how much data was it based upon?
Have they continued to update the model as parts are being tested?
How much do you trust it?

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get the "final word" from the
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Do I have a specific waveform, no.  I am asking a general question
about the S3.  Just how sensitive it really is and what precautions do
I need to take to make it work.  Because each layout is different, the
loading can be anything if you consider all of the failure modes.

Ask the hotline, you may be surprised and pleased
lecroy,

See below,

Austin

lecroy wrote:

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back to the driver do to the driver,
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of the 200+ hotline CAEs to get
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you get multiple answers...) It
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their mistakes, and improve their
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the loop!
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Unfortunate.  If you don't ask, you don't get an answer.  Try it.  If it doesn't
work, let us (me) know.  You
must prefer doing everything the hardest way possible.  We also do not
appreciate the slamming of our hotline
staff.  Theya re all dedicated to helping our customers succeed, as that is what
sells parts, not "closed
cases."  If a hotline engineer can not resolve the problem within a fixed amount
of time, it is escalated.  Once
escalated, it then goes up the ladder til it reaches someone who can resolve the
issue.

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the output pin to a voltage that is
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really hard for the reflection to
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excursions are, an be sure they stay
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You can not even probe, nor observe the points that are in question here.  The
VNA is a frequency domain tool,
and unless you convert the S parameters into their transient form (done by some
advanced simulators) you will
learn nothing at all (even after simulating or trying to measure).  "Real" only
applies to this one part.  What
about the next one?

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The test chips from UMC that had all of the transistors on them and
characterized.

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Yes.  That is the procedure.

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Better than the real silicon, which may be from any yielding corner, and not be
representative of the worst
possible cases (fast, cold corner, with hi-voltages for example.  You can not
buy a fast corner IO transistor
version of the chip, you have to simulate it.  Folks who submit their chips to a
third party for IBIS models do
their customers a terrible dis-service, as the model is only as good as the
sample of chips sent, which is
ususally terrible.

We must support our devices through accurate and useful models.  Fact of life
(and business).

The models are an IOU:  that is what we tell you you will get.

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get the "final word" from the
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General Answer:  simulate it, and make sure it meets yourt needs, and our
operating and abs max specifications.

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Already stated, if you exceed the abs max specs, you may find that more than .1%
of the parts do not last the
intended operating life.  Good Signal Engineering practices will result in a
robust design that will meet all
goals, and all specs and last a long, long time.

A car manufacturer was once asked, "what is the safest way to use your vehicle?"
 The answer:  "don't use it at
all.  Just park it, and walk away."

So ask questions that can be answered, like sending me a plot of what you think
might be a problem.  Or logging a
call to the hotline (and then letting us know if you are not completely
satisfied with the answer).


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Failure mode is simple:  the stress on the pmos output device when the IO pin is
used as an input shall not
exceed that stated in the abs max spec (4.05V for example on Virtex II Pro and
Spartan 3, +3.75V abs max Vcco,
and -0.3V abs max Vio on the io pin).  If this stress is exceeded, it will
eventually cause the IO to become
leaky (ie > 10uA IOB leakage current spec will be violated).  This increase in
leakage may, or may not affect
your system.

Simulate and you will see......




Re: Ask the hotline, you may be surprised and pleased

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If you go outside the limits with Vio and are current limited
to 10uA will there be a problem?  How about 100uA?  1mA?

Please excuse my ignorance on this stuff....



Re: Ask the hotline, you may be surprised and pleased
Tim,

Since this is an input, there is no current going into/out of it (unless
you go to the clamp diode limit).

So assuming that the diodes are not clamping, it is purely a voltage issue.

No ignorance here at all, the effect that is actually seen (with tests at >
4.5V) result in increased leakage, but no functional failure of the IOB (it
still works, but does not meet the < 10uA IO pin spec).

This is the subject of research and PhD thesis material among the
technology communities.

Austin

Tim wrote:

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