Xilinx RAM64x1D simulation problems

When I try to simulate writing into a RAM64x1D, the output (signal "douta") becomes indeterminate. My testbench file and instantiation file are in the text that follows. Am I doing something wrong, or is there a problem with the Xilinx simulation libraries?

Thanks, Doug

---------------- Cut Here -----------------------------

-- TestBench Template

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_signed.ALL;

library unisim; -- required for Xilinx components instantiated in the design

use unisim.vcomponents.ALL;

ENTITY dp64x1d_tb IS

END dp64x1d_tb;

ARCHITECTURE behavior OF dp64x1d_tb IS

component dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end component;

signal rst : std_logic;

signal clk : std_logic;

signal wr_en : std_logic;

signal in_addr : std_logic_vector(5 downto 0);

signal din : std_logic;

signal douta : std_logic;

signal out_addr : std_logic_vector(5 downto 0) := "000000";

signal doutb : std_logic;

constant CLK100_HALF_PERIOD :time := 5 ns; -- 100 MHz

begin

clk100MHz_proc: process

begin

clk in_addr,

din => din,

douta => douta,

-- Output side

out_addr => out_addr,

doutb => doutb

);

-- ---------------------------------------------------------------

-- Generate the rst pulse

---------------------------------------------------------------

rst_proc: PROCESS

BEGIN

-- Reset the core

rst clk,

WE => wr_en,

D => din,

A0 => in_addr(0),

A1 => in_addr(1),

A2 => in_addr(2),

A3 => in_addr(3),

A4 => in_addr(4),

A5 => in_addr(5),

DPRA0 => out_addr(0),

DPRA1 => out_addr(1),

DPRA2 => out_addr(2),

DPRA3 => out_addr(3),

DPRA4 => out_addr(4),

DPRA5 => out_addr(5),

SPO => douta,

DPO => doutb

);

end rtl;

------------------------------- end ---------------------------------

Reply to
Doug Miller
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OK, just got a little stranger - I ran this at home on my free Xilinx Edition Modelsim, and it ran fine. At work, I have Modelsim PE, which generates the indeterminate output. Does this mean that I need to recompile my Xilinx Unisim library on PE?

Doug

"douta")

the

design

-
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Reply to
Doug Miller

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