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Xilinx PMCD+DCM reset question...

In looking at the Virtex-4 documentation for the PMCD, Xilinx shows a simple connection from the DCM to the PMCD. They don't show the clocking for the reset signal going into the PMCD even though the Xilinx doc says that the reset should be released synchronously to with the clock.

If the DCM and the PMCD both get the same reset signal, I assume that since the DCM output clocks should be stopped while reset is asserted, inherently the release of reset will be synchronous to the clock since the clock won't be running at the time.

Does this match other people's understanding?

Thanks!

John Providenza

Reply to
johnp
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John,

Yes.

The PMCD is simply some D type flip flops, with a delay matched path for the 1X output. If the phases of the divided clocks are important, then reset of the PMCD is useful. If the phases are not important, don't even bother with the reset of the PMCD. When the PCM input clock is driven by the DCM, one should not worry about the reset, as you say, the DCM will not do anything 'bad' to the PMCD while reset is asserted.

Aust> In looking at the Virtex-4 documentation for the PMCD, Xilinx shows a

Reply to
Austin Lesea

Austin -

Thanks for the clarification.

John Providenza

Aust> John,

Reply to
johnp

Yes.

In addition, please make good use of "RST_DEASSERT_CLK" and "EN_REL" when you are worry about phase.

Ricky

Aust> John,

Reply to
Ricky Su

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