Xilinx PCIe endpoint core minimalistic design

Hello,

I am implementing a PCIe design for the HiTechGlobal HTG-V4-PCIe60 (Virtex 4 FX60 and FX100) board and having a little difficulty. What I'm trying to do is create a minimalistic base design that will eventually be used to build larger applications. The basic idea is to get the host system to see the card on the PCIe bus via a probe. I do not want to handle transactions or any other functions unless it is necessary for the board to be seen by the host. Drivers (kernel modules) for the card is planned to be done later as well.

I am using the Xilinx pci_express_v3_4 8-lane endpoint core, which comes with an example design and scripts to implement it. After modifying to the UCF, the example design work with no problem but I would like implement my own design using ISE. In an ISE project I have included the pci_express_v3_4.ngc file and created a top level module that instantiates the core (instantiation code provided by Xilinx). The top module includes all PCIe interface signals for the 8- lane core, transaction signals (rxn and txn), and configuration signals that are illustrated in the Xilinx LogiCORE PCI Express v3.4 Users Guide. I deasserted a the majority of the configuration signals since asserting would cause interrupts, error reports, etc. Uploading the design as-is does not work, so clearly I am missing something.

Unfortunately I haven't been able to find a Xilinx document that details exactly what is needed to get the PCIe core to work. What signals must be present and what values must they hold? Does there have to be a transaction handler present even though there are no transactions to be handled? Must the core's input signals be assigned a value or could we justs let ISE set a default? What values do I need to set the configuration signals at startup? What I'm looking for is the bare minimum. Some document (or someone) that outlines the procedure (and "must haves") for a minimalistic ISE design using the endpoint core. Does such a document exists?

Like I said before, I just want the host system to see the board on the bus. Transactions and all other functionality will be handled later.

Does anyone know what I need to do or have some useful techniques (ideas, documents, links, etc.) than could help me?

Reply to
spacegato
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I don't have any experience with PCIe cores, but for PCI the core needs to be able to handle configuration cycles (at least) in order for the BIOS to probe the device. So basically most of the functionality required for transaction processing must be in place in even a minimal design.

If I were you I'd instantiate a fully functional/connected core and work backwards from there...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Reply to
Mark McDougall

Thanks. I took your suggestion and created a full design using Xilinx's example design and ISE. After I got that working I just removed the pieces that I didn't need. The funny thing is that I got pretty much the same design as I had originally with the exception a buffer attached to sys_reset_n and the following for clock management settings.

defparam sys_clk_mgt.SYNCLK1OUTEN = "ENABLE"; defparam sys_clk_mgt.SYNCLK2OUTEN = "DISABLE";

Well....lesson learned.

Thanks again.

Reply to
spacegato

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