Xilinx PCIe 8-lane endpoint constraints

Hello,

I am fairly certain the main reason for the "requirement" is because Xilinx IP Solutions has a validation platform with all eight lanes on one side of the FPGA. Xilinx guarantees what is listed in the datasheet, and it's prudent (as you can imagine) for Xilinx invest significant time in testing complex IP cores such as this one.

Other topologies are possible. Three considerations come to mind, there may be others:

1. Using both sides requires that you distribute a common MGT reference clock to BOTH sides of the device on the PCB. Typically, this would be a clock derived from the 100 MHz reference on the PCIe connector.

1. Using both sides *may* make it more difficult to meet timing (that's not a promise, just something to think about). For instance, the physical layer is now having to stripe/assemble the data streams to/from MGT on opposite sides of the device.

2. You will require some IP core options that may not be available for general use through Core Generator. Specifically, the channel bonding signals that run between MGT need to be pipelined where the signal from the master crosses the device horizontally to the slaves on the other side. You may be familiar with the MASTER, 1HOP, and 2 HOP attributes for the channel bonding behavior. In addition to attribute changes, it also requires a connectivity change.

If you have serious interest (versus "just curious"), I encourage you to follow up with Xilinx through your FAE or distributor. Eric

Eric Crabill schrieb:

Nope. The datasheet contains no information on placement at all. There is an answer record that adds restrictions on the placement of the rocket IO, the clock input, and the location of the DCM used. Heaven knows why the datasheet is not updated once an answer record like that is created.

Kolja Sulimma

Kolja

you arent born yesterday - so you should have figured out by now that NO ONE at Xilinx could possible think that anyone would be designing an PCIe 8 lane design without having Xilinx FAE holding his hand.

There are many many things 'to know' that are somewhere but almost impossible to find. The MGT channels bonding is defenetly one of the most complicated things to get ever right so I am not wondering at all that all information that is there about the channel bonding constraints isnt there in the main datasheet.

I have given up any assumptions what one may think is possible - whenever you have a design you must run it through the toolchain and see if it passes with no warnings - any attempts to get pin assignemnets and other simple things done correct by reading the datasheets - NO WAY. You may get lucky a few times, but one day you desing some thing by only datasheet info that defenetly want work because some strange constraints.

in V4FX12 no IOB in right half of the die can reach any DCM input legally - there is no route! is that in datasheet?

If you havent made commitments to buy PCIe IP core maybe you can retarget V5LXT - the 8 lane board ML558 is real, you should possible get even the schematics from your FAE, so it would be safe path, well of course it depends on your target deadlines.

I bet Xilinx is interested to have more real V-5 based products out as fast as posssible to have more 'showcase' for the leading edge technology, so talk to them directly, maybe the V5LXT solution can be arranged in your timeframe

Antti