Xilinx PCI Express Solution: 2 Questions.

Dear Xilinx (and others with RocketIO/X, PCIe experience),

I am very interested to know how the Xilinx PCIe Solution works. As far as I have been able to determine there are several problems:

1) Rocket IO does not have direct control of TX enable,

PCIe TxElecIdle is specified as Vdiff50 UI

Xilinx PCIe documentation (at least all the documentation what is available) does not indicate that any external "helper-workaround" electrical hardware is required to make the rocketio PCIe compliant.

So the question is how does it work ?

2) PCIe specification requires the clock tolerance (for transmit) to be no more than +-300ppm, that means of course that on the receive side the CDR has to lock to signal that has worst case error of +-300ppm

But that is outside the lock range for rocketio CDR ? Both rocketIO and X specify that offset to be in range +-100ppm, the PCIe requirement to accept +-300ppm is way beyound that!

So the question is how does it work ?

From Xilinx PCIe IP Core datasheet: "The core design is verified using the Xilinx proprietary test bench."

Does the test bench really model the transmition line electrical characterisctics - including the AC capacitors, and does it test with worst case +-300ppm offset clock rates ?

NiTal has PCIe development boards that all use Virtex2Pro, so I assume the PCIe can be implemented with RocketIO, question is what tricks are used to make the rocketIO PCIe compliant?

/Antti Lukats

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Antti Lukats
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