Xilinx PCI-express coregen

There are some MAXDELAY=1ns constrain for TX signals inside PCIE coregen. eg: (* MAXDELAY="1.0" *) wire [1:0] tile0_txcharisk0_r; (* MAXDELAY="1.0" *) wire tile0_txdetectrx0_r; (* MAXDELAY="1.0" *) wire tile0_txelecidle0_r; (* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispmode0_r; (* MAXDELAY="1.0" *) wire [15:0] tile0_txdata0_r; (* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispmode1_r; (* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispval1_r; (* MAXDELAY="1.0" *) wire tile0_txdetectrx1_r; (* MAXDELAY="1.0" *) wire [19:0] tile0_txdata1_r; (* MAXDELAY="1.0" *) wire tile0_txelecidle1_r;

but,my core_clk is 4ns(250MHz) and user_clk is 8ns(125MHz). does it still meet the MAXDELAY=1ns timing requirement?

Reply to
water9580
Loading thread data ...

The MAXDELAY is an attribute for a net route and has nothing to do with clocks. From the driver of this net to the destination, the place & route must keep the delay under a nanosecond or it WILL report a timing violation.

You can even use MAXDELAY attributes on clockless logic.

Reply to
John_H

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.