Xilinx Partition for EDIF Flow (synthesis synplify)

You can synthesize in parts leaving your lower module(s) as black boxes in the top level. Just leave the source for the lower module that you want a separate edif for out of the file list in the top level project, and then create another project with that module as the top level. Make sure you disable i/o insertion and clock buffer insertion for your lower level module, otherwise xilinx will throw an error when it tries to stitch the edifs together.

Thanks Ray.

I tried that, generating 2 seperate edf files for the top and lower-level module. And I put // synthesis syn_black_box on the stub module in the modified top-level design. But when I put both edf files into ise, it complains cannot have 2 source files. I must have missed out something, probable due to my limited Verilog.

Just to c> snipped-for-privacy@gmail.com wrote:

John,

I did that, but I can't set partiti> Try specifying only the top level edif file and include a macro search

You are close. In ISE you only specify the top level design's edif. The rest of the edifs have to be in the directory pointed to by the path property (I think that is under the translate properties). Make sure the edifs have the same name as the name of the black box and are in that directory. If you do that, then ISE will stitch them into the design.