Hi, I am using Xilinx ISE for PAR (from edf to bit file). and synplify tool for synthesis (to generate edf). Is there some thing like incremental PAR or incremental SYNTH. Please give some reference. Thanks, Vittal
I know that incremental PAR is possible with Xilinx ISE. The method used is to first go through the entire flow once. Then use the result from this flow as "Guide files" for subsequent flows.
You may want to look at the Xilinx documentation for more details. Also take a look at this.
-Sudheendra Kadri
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