1. Home
  2. Field-Programmable Gate Arrays
  3. Xilinx PAR problem when using chipscope

Xilinx PAR problem when using chipscope

Hi

I have design that will PAR fine when chipscope is not included but whe it is I get the following error :-

The placement constraints of the IOBs app_rd_n and app_AD[7] makes thi design unroutable due to a physical routing limitation. This device has shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be drive by the same signal or one of the signals will be unroutable. Befor continuing please remove the placement constraints or move one of thes IOBs to a new location.

Has anyone had this problem and found a way around it.

Thanks

Reply to
maxascent
Loading thread data ...

Hi Jon, This is maybe because the tools have mapped FFs into a pair of IOBs that then require too many clocks for the routing resource available. The chipscope instantiation has probably added an extra IOB FF that's caused this problem. Try turning off the 'Pack I/O Registers/Latches into IOBs' option in the Map tool. HTH., Syms.

Reply to
Symon

Thanks Syms that has solved the problem.

Jon

Reply to
maxascent

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.