Xilinx padding LC numbers, how do you feel about it?

...snip...

If I were you, I wouldn't worry too much about Austin. He is pretty knowledgeable techincally even if his work with the customer leaves something to be desired. I will say that with some of the stuff that Austin posts, you would think he was a conspiracy theorist.

You have posted your concerns and have gotten some responses. The resonse from X seems to be a lot like the way they responded to the data sheet LC count issue in the past. You are not likely to get anything further out of them at this point. As you post more you just feed the trolls (or become one).

Reply to
rickman
Loading thread data ...

yep ... the several threads have been useful to discuss difficult problems that Reconfigurable Computing faces with regards to strict IP limitations these folks require, and effectively prohibt open source development with.

Calling them to task for heavily using open source in their products, while agressively prohibting open source development for their product line will no doubt hit nearves that may over time lead all the FPGA companies to actually open up to a reasonable degree and reap the rewards of extensive open source development which supports their all sales and greatly enhances their product offerings.

Those that leach off open source, while completely blocking open source development for their products, need to be called on the carpet for that, and probably regularly till they get the hint that open source is a TWO way relationship -- they need to give as much IP as they take.

Reply to
fpga_toys

I suspect that many of those entities that "leech off of open source" don't really care. See, for example, Microsoft.

I realize that Xilinx makes heavy use of Cygwin, tcl and various other open-source technologies. Unfortunately (for those with certain points of view, at least), I don't see that there's any obligation on Xilinx's part (or my part, for that matter) to "give back to the community."

It's perfectly all right for you to choose to give away your work, and it's equally all right for me to choose not to do so. It is NOT all right for someone to demand that others give away their work, even if that work was created using free/open-source tools.

I am grateful to Stallman for creating emacs, and grateful to the subversion folks for their tools, as I use them every day. That I use these tools to create proprietary designs sold at a profit by my employer is not relevant. You said it yourself, although in a different context: I like my home and I like my house.

-a

Reply to
Andy Peters

and it's not alright for Xilinx to let an open source project proceed for many months, and then shut it down without fair compensation. I suspect Xilinx was fully aware of the projects open source nature, since the SF project which was created on 4/17/04 and the talks in June and Sept where all clear about being open source.

The WHOLE reason behind FSF and GPL is EXACTLY the highly restrictive ISE licenses. I almost couldn't stop rolling on the floor when Xilinx was puffing behind their donations to FSF. It would make a great poster, giant Xilinx paying FSF so it's ok to NDA lock their entire poduct line ... some how I would guess that Richard wouldn't think that is politcally correct to hide behind the FSF that way. Should probably ask some day.

Reply to
fpga_toys

All,

It is unfair to the university(ies) or school(s) involved, and also unfair to the company(ies) involved to continue with these allegations.

You may be harming the student(s), professor(s) and potentially the company(ies) involved.

We sponsor research, and we have many interns. We contribute to many schools and universities a substantial amount of products and software.

We do not sponsor research that gives away our intellectual property.

We expect our licenses, IP, and rights to be respected.

Thank you,

Austin

Reply to
Austin Lesea

I agree, more than you might realize. Letting open source projects proceed which violate your IP is very poor management, both on the Xilinx side, and on the educational side. You might have noticed that I've also very clearly stated that open source should not violate Xilinx IP either.

It's more than obvious from these discussion that a very large portion of your user community in this forum clearly does not understand the extent that Xilinx wishes to protect it's IP, and what is, and is not acceptable disclosure outside the very restrictive NDA that is part of the ISE (and all Xilinx) software.

I believe it's quiet fair to critize Xilinx for it's heavy use of open source software, while locking all access to it's ISE tool chain with strict NDA. That violates the vary rationale behind the creation of GPL software that you benefit from.

But that aside, the question remains, just what, if any, legal interfaces may open source software use to augment the IDE tool chain? The strictest reading of the license and NDA is clear ... NONE. Since Xilinx stopped that JHDLBits project from releasing, after many very public months of work, it's only fair to ask that Xilinx reconsider it's NDA boundries and consider that open source development may well greatly enhance the Xilinx product offerings over the next several years in ways that are difficult to fully describe today.

If the official answer in absolutely none, as the terms of the current license require, that is fine ... and I will clearly state so in the FpgaC project and remove all Xilinx interfaces so Xilinx IP rights are not violated.

Reply to
fpga_toys

John,

I am not a lawyer.

But it seems clear to me, when I read it: the answer is "none."

To imply otherwise is clearly misleading, and could be interpreted as intentionally causing harm (to Xilinx, or its partners, or its customers).

A retraction on your part would be completely acceptable, and your statement that you will immediately cease and desist the use of our tools against the agreement you signed is most welcome.

For anyone seeking to do anything that they are unsure about, I suggest you contact our legal staff.

formatting link

Austin

Reply to
Austin Lesea

Agreed. The Xilinx license prohibits open source development using any internal ISE documentation or interfaces. I hope this discussion has been pretty clear to those claiming that XDL and the associated libraries are fair game for open source development.

Retract what? You have only confirmed my most damming statements, that Xilinx freely takes a windfal profit from open source IP while completely locking out open source development for FPGA tool chains. Exactly the corporate behavior that many cry as foul in the open source movement, and directly counter the founding principles in the Free Software Foundation. But that is your right.

My statement was that we would not introduce XDL or other Xilinx proprietary IP into FpgaC. I will continue to use my Xilinx IP for my own use, as I suspect most of our developers and users will.

That Xilinx wishes to continue locking open source development out of ISE and other Xilinx software is your right. I think everyone here is clear about that now, and will react accordingly. The big problem is that if this many knowledgable people in this forum are clueless about your IP and the obvious restrictions against open source, then you really need to work on getting the word out to avoid another JHDLBits meltdown that will really sour Xilinx's reputation in the open source community.

Reply to
fpga_toys

John,

I am glad to hear you will comply with our licensing agreement.

As for your other comments, I am silent. It is your right to rant (and rave).

But not to say anything damaging.

Austin

Reply to
Austin Lesea

I have to say that I am pretty clueless about this JHDLBits issue. I am aware that Xilinx does not support any open source development, but are you saying they took legal action to shut down an open source project? Can you provide any details? Was it making use of some of their software or was the complaint just that it was reverse engineering the parts?

Can Xilinx stop you from reverse engineering the parts?

Reply to
rickman

see the second post in "So what happened to JHDLBits?"

data contained in an ISE release, Yes ... breach of contract.

But, I'm not a lawyer as should be assumed, and you should see your own counsel.

Reply to
fpga_toys

A couple of weeks ago I noticed an old pen on my desk from ClearLogic that made me wonder if they were still in business. "Just Send the Bitstream" "Samples in 2 Weeks" "The FPGA Alternative." This company took Altera bitstreams and generated masked logic. When I went googling into the situation, I came across the legal papers that were written after the company shut down and was taking care of some of the details.

That legal opinion underscored that reverse engineering devices to understand the implementation is an acceptable practice. Copying a section of a mask is not. The software is a different issue. The Altera licensing specifically declared the bitstream as proprietary and that using that bitstream directly to produce knockoffs was in violation of the agreement.

You can reverse engineer parts. You don't necessarily have the right to manipulate files (or bitstreams) that are part of licensed software. Or at least that's my interpretation of the Judges' opinions.

- John_H

Reply to
John_H

Rick,

email me.

Austin

Reply to
Austin Lesea

It's ok. I don't have any real interest in reverse engineering FPGAs or using Xilinx software for anything except designing parts.

If you really want to help me with a real issue, see what you can do to get modular reconfiguration for the Spartan parts. I guess this is not used by many and is even less asked for on the Spartan parts. But a design I wanted to do pretty much required modular reconfiguration. I looked into it and found that the tools were pretty primitive and likely buggy, but it might have worked out. Then I found that support for the Spartan 3 was not available. When I inquired with some people at the factory I was told that Xilinx was "committed" to making this available for the S3 parts. But it never happened.

At one point it seemed like the V4 parts might make this happen since they also have the issue of no tbufs. I have not checked in a long time, but AFAIK modular reconfiguration is not supported for Spartan 3 parts.

BTW, what I mean by modular reconfiguration does not mean the part is running, as in partial reconfiguration. I believe there are some limitations with the S3 hardware that prevent this. I wanted to partition a design into blocks and depending on what hardware is attached to the FPGA, different interface blocks would be loaded into the FPGA to mate with that hardware. This would all be done at configuration time, not after the part is running. This way the FPGA design can be managed in a modular fashion rather than needing dozens if not hundreds of different downloads for the various permuations of hardware.

Any chance with the Spartan 3?

Reply to
rickman

Rick,

Afraid not. Spartan folks are just not into reconfiguring, unless it is the whole bitstream. Seems they polled their customers, and even though they have shipped 10 million S3's to date, they see no need...

So for S3, no.

Don't know about Spartan 3E.

Now in V4, partial is supported, and even partial while running is supported (sort of, but most would say that you have to be a pretty expert user to do it right now).

The SDR developers are way ahead in this, and they pretty much have to have it working, so since V4 is the choice for SDR platforms, we are busy busy busy with the tools and support.

Austin

Reply to
Austin Lesea

Yeah, that's what I figured. Next time I'll get it in writing before I believe a promise about support. Hmmm... actually I did have it in writing if you count email.

Aust> Rick,

Reply to
rickman

Well, the SNOWPLOW register is still there in S3E, right?

I mean, it's not a walk in the park, but after Atmel and Virtex it's the next best thing (are you listening, Actel?) ;)

- a

--
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380
Reply to
Adam Megacz

Ugh, after this messy thread I think I'm going to be afraid to utter the phrase "open source" in the presence of Xilinx people at FPGA'06. Please understand that fpga_toy's attitude is very, very far from being typical of the people who actually make the big open source projects work.

Richard Stallman was on campus a few months ago, and I spoke to him about the possibility of a "GNU Gateware Compiler" under the GCC umbrella. His response was quite positive, although after explaining the current bitstream situation it dimmed considerably. Even so, he remained eminently calm and never hostile or even indignant. I was quite impressed.

My opinion is that it's just a matter of time before one of the vendors opens the bitstream format of one of their low-end devices (or Atmel comes out with a bigger device -- same effect). Personally, I'd much rather see it be Xilinx -- that would be convenient for me in a number of ways. But ultimately I'll be jumping on whichever boat leaves the pier first, likely taking a lot of impressionable young undergrads with me... ;)

Cheers,

- a

--
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380
Reply to
Adam Megacz

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.